Moore’s Law Propounded by Gordon Moore in the 1960’s Predicts that the complexity of ICs increases exponentially Caused by a steady decrease in minimum feature size Produces increases in speed Moore’s Law is the reason microelectronics has dramatically changed our lives in the last three decades

CMOS is the dominant Si technology because of area and power Silicon CMOS Si is the dominant technology, because of silicon dioxide - Other materials include GaAs, GaN, SiGe, SiC for specialized applications CMOS is the dominant Si technology because of area and power - Bipolar important for niche applications - more than 90% of all semiconductors today are Si CMOS

IC Evolution ULSI – Ultra Large Scale Integration (1990) 107 – 109 Giga-Scale Integration (2005) 109 – 1011 Tera-Scale Integration (2020) 1011 - 1013

Moore’s Law Electronics, April 19, 1965.

Evolution in Complexity

Transistor Counts 1 Billion Transistors K 1,000,000 100,000 10,000 Pentium® III 10,000 Pentium® II Pentium® Pro 1,000 Pentium® i486 i386 100 80286 10 8086 Source: Intel 1 1975 1980 1985 1990 1995 2000 2005 2010 Projected Courtesy, Intel

Moore’s law in Microprocessors 1000 2X growth in 1.96 years! 100 10 P6 Pentium® proc Transistors (MT) 1 486 386 0.1 286 Transistors on Lead Microprocessors double every 2 years 8086 8085 0.01 8080 8008 4004 0.001 1970 1980 1990 2000 2010 Year Courtesy, Intel

Die size grows by 14% to satisfy Moore’s Law Die Size Growth 100 P6 Pentium ® proc Die size (mm) 486 10 386 286 8080 8086 8085 ~7% growth per year 8008 ~2X growth in 10 years 4004 1 1970 1980 1990 2000 2010 Year Die size grows by 14% to satisfy Moore’s Law Courtesy, Intel

Lead Microprocessors frequency doubles every 2 years 10000 Doubles every 2 years 1000 P6 100 Pentium ® proc Frequency (Mhz) 486 10 386 8085 8086 286 1 8080 8008 4004 0.1 1970 1980 1990 2000 2010 Year Lead Microprocessors frequency doubles every 2 years Courtesy, Intel

Minimum Feature Size Trend From S. E. Thompson, Sub-100 nm CMOS, IEDM 1999 Short Course

MOS TRANSISTOR

Feature Size The ratio of minimum allowable value of gate width(W) and gate length(L) is called as minimum feature size. Thus feature size is function of IC technology. N-MOSFET layout

VLSI Tech: CMOS Key feature: transistor length L 2002: L=130nm

FABRICATION PROCESS

Fabrication of MOS Transistor The MOS fabrication process consists of Wafer preparation Several steps of photolithography Etching Oxidation Diffusion Ion Implantation Deposition

Diffusion Ion Implantation Deposition

Step 1: Obtaining the Sand The sand used to grow the wafers has to be a very clean and good form of silicon. For this reason not just any sand scraped off the beach will do. Most of the sand used for these processes is shipped from the beaches of Australia. Sand is primarily acquired from the beaches of Australia. Video will mention sand quality

FABRICATING SILICON Quartz, or Silica, Consists of Silicon Dioxide Sand Contains Many Tiny Grains of Quartz Silicon Can be Artificially Produced by Combining Silica and Carbon in Electric Furnace Gives Polycrystalline Silicon (multitude of crystals) Practical Integrated Circuits Can Only be Fabricated from Single-Crystal Material

Step 2: Preparing the Molten Silicon Bath The sand is taken and put into a chamber where it is heated to about 1600ºC where it melts. The molten sand will become the source that will ultimately produce the raw poly-crystalline silicon. The CZ method discussed on pg 54 is where this discussion is going

Raw Polysilicon Raw polycrystalline silicon produced by mixing refined trichlorosilane with hydrogen gas in a reaction furnace. The poly-crystalline silicon is allowed to grow on the surface of electrically heated tantalum hollow metal wicks Content standard 3 of Chemical reactions is introduced here.

Creating the Single Crystalline Ingot Crushed high-purity polycrystalline silicon is doped with elements like arsenic, boron, phosphorous or antimony and melted at 1400° in a quartz crucible surrounded by an inert gas atmosphere of high-purity argon. The melt is cooled to a precise temperature, then a "seed" of single crystal silicon is placed into the melt and slowly rotated as it is "pulled" out. Content standard 3 of Chemical reactions is continued here.

Step 3: Making the Ingot A pure silicon seed crystal is now placed into the molten sand bath. This crystal will be pulled out slowly as it is rotated. The result is a pure silicon tube that is called an ingot The CZ method is now being explained. The slides come from the url http://entcweb.tamu.edu/zoghi/semiprog/INDEX1.HTM material preparation. The text covers it on pg 54 - 57

Creating the Single Crystalline Ingot (cont.) The surface tension between the seed and the molten silicon causes a small amount of the liquid to rise with the seed and cool into a single crystalline ingot with the same orientation as the seed. The ingot diameter is determined by a combination of temperature and extraction speed Content standard 3 of Manufacturing in Engineering Technology is introduced here.

CYLINDER OF MONOCRYSTALLINE The Silicon Cylinder is Known as an Ingot Typical Ingot is About 1 or 2 Meters in Length Can be Sliced into Hundreds of Smaller Circular Pieces Called Wafers Each Wafer Yields Hundreds or Thousands of Integrated Circuits

Ingot Sizes Most ingots produced today are 150mm (6") and 200mm (8") diameter, For the most current technology 300mm (12") and 400mm (16") diameter ingots are being developed. Content standard 3 of Manufacturing in Engineering Technology is continued here.

Ingot Characterization Single Crystal Silicon ingots are characterized by the orientation of their silicon crystals. Before the ingot is cut into wafers, one or two "flats" are ground into the diameter of the ingot to mark this orientation. Crystal orientation is covered on pg 59-62

Step 4: Preparing the Wafers The ingot is ground into the correct diameter for the wafers. Then it is sliced into very thin wafers. This is usually done with a diamond saw. Content standard 3 of manufacturing in Engineering Technology is continued here. WWW.fullman.com covers this well

WAFER MANUFACTURING The Silicon Crystal is Sliced by Using a Diamond-Tipped Saw into Thin Wafers Sorted by Thickness Damaged Wafers Removed During Lapping Etch Wafers in Chemical to Remove any Remaining Crystal Damage Polishing Smoothes Uneven Surface Left by Sawing Process http://www.xensei.com/users/adex/prodtech/silicon_wafer.html

Some wafers in storage trays

Growth of Epitaxial Silicon The purpose of EPI growth is to create a layer with different, usually lower, concentration of electrically active dopant on the substrate. For example, an n-type layer on a p-type wafer. This layer is of a much better quality then the slightly damaged or unclean layer of silicon in the wafer It is called the Epitaxial layer - where the actual processing will be done. Content standard 3 of Chemical Reaction in Chemistry is continued here. WWW.fullman.com covers this well

An Epitaxial reactor.

Diffusion Diffusion is often two step process - The first step is called predeposition and comprises the deposition of a high concentration of the required impurity. The impurity penetrates some tengths of a micron into a silicon at a temperature of 800 to 1200 deg. Silicon atoms in the lattice are then substituted by impurity atoms. The second step is drive-in diffusion. This high temperature step decreases the surface impurity concentration and forces the impurities to penetrate deeper in to the wafer.

Implantation The ion implantation(doping in MOS process) takes place in an ion implanter which comprises a vaccum chamber and an ion source which can emit phosphorous arsenic or boron ions. Silicon wafers are placed in a vacuum chamber and the ions are accelerated into the silicon under the influence of electric and magnetic field. The penetration depth depends on the ion energy. Ion implantation is characterized by the following parameters : the type of ions the accelerating voltage the current strength the implementation duration

Ion Implantation

Etching There are several etching techniques:- Wet-etching: wafer is immersed in a chemical etching liquid. The process is isotropic - etching rate is same in all directions. Dry-etching: both physical and chemical processes are used. The process is anisotropic - etching is limited to one direction due to the perpendicular trajectory of the employed ions at the wafer surface. Plasma-etching: wafers are immersed in a gaseous plasma formed from inert gas (orgon) and chemical reactants that etch SiO2.(Reactive ion Etching) Sputter-etching: wafer is bombarded with the by gas ions such as Argon(Ar) which physically dislodge atoms at the wafer surface.

Plasma Etchers

Photolithography Photomasks and Reticles Examples of 5X Reticles:

Photolithography Photomasks and Reticles Once the mask has been accurately aligned with the pattern on the wafer's surface, the photoresist is exposed through the pattern on the mask with a high intensity ultraviolet light. There are three primary exposure methods: contact, proximity, and projection.

Lithography

Pattern Transfer From Mask To Wafer exposed Si3N4 Photo resist layer SiO2 WAFER Removal of the photo resist layer Development of the photo resist Etching of the nitride Masking + exposure Coverage with photo lacquer Exposed Photo resist Wafer + Oxide (or Nitride)

Silicon Wafer and Chips

IC Packaging

Requirements to package Protect circuit from external environment Protect circuit during production of PCB Mechanical interface to PCB Interface for production testing Good signal transfer between chip and PCB Good power supply to IC Cooling Small Cheap

Traditional packages DIL (Dual In Line) PGA (Pin Grid Array) Low pin count Large PGA (Pin Grid Array) High pin count (up to 400) Previously used for most CPU’s PLCC (Plastic leaded chip carrier) Limited pin count (max 84) Cheap SMD QFP (Quarter Flat pack) High pin count (up to 300) small

New package types BGA (Ball Grid Array) CSP (Chip scale Packaging) Small solder balls to connect to board small High pin count Cheap Low inductance CSP (Chip scale Packaging) Similar to BGA Very small packages Package inductance: 1 - 5 nH

New Transistor Structures Lateral Asymmetric Channel Silicon-on-Insulator (SOI) SiGe Metal Gate FET Single Electron Transistor

Silicon-on-Insulator (SOI) Active silicon on a thick insulator (SiO2) Mainstream technology of the future?

Silicon-on-insulator CMOS The CMOS processes require rather deep n-well and/or p-well diffusion to achieve low threshold voltage ( 1V). The resulting lateral diffusions necessitate relatively large spacing between p and n type transistors. The resulting increase in IC area can be avoided. This gives complete isolation of nMOS and pMOS transistors removing the possibility of latch up. n+ n- p+ p- nMOST pMOST Isolating substrate

SOI Advantages Faster Latchup-proof Less short channel effects Better suited to low-voltage & low-power needs More compact 3-D integration But ... SOI wafers are expensive Floating body effects, eg “kink”

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