Delays in Verilog Programmable Logic Design (40-493) Fall 2001

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Presentation transcript:

Delays in Verilog Programmable Logic Design (40-493) Fall 2001 Computer Engineering Department Sharif University of Technology Maziar Gudarzi

Introduction Delays are crucial in REAL simulations Delay Models Post-synthesis simulation Post-layout simulation FPGA counter-part: Post-P&R simulation Delay Models Represent different physical concepts Two most-famous models Inertial delay Transport delay

Delay Models Delays in Verilog

Delay Models Inertial Delay The inertia of a circuit node to change value Abstractly models the RC circuit seen at the node Different types Input inertial delay Output inertial delay

Delay Models Transport Delay Represents the propagation time of signals from module inputs to its outputs Models the internal propagation delays of electrical elements

Delay Types Delays in Verilog

Delay Types Rise Delay Fall Delay Turn-Off Delay Min/Typ/Max Delay values

Delays in Gate-Level Modeling Delays in Verilog

Delays in Gate-Level Modeling Delay are shown by # sign in all verilog modeling levels Inertial rise delay Inertial fall delay Inertial turn-off delay and #(rise_val, fall_val, turnoff_val) a(out,in1, in2)

Delays in Gate-Level Modeling (cont’d) If no delay specified Default value is zero If only one value specified It is used for all three delays If two values specified They refer respectively to rise and fall delays Turn-off delay is the minimum of the two

Delays in Gate-Level Modeling (cont’d) Min/Typ/Max Values Another level of delay control in Verilog Each of rise/fall/turnoff delays can have min/typ/max values not #(min:typ:max, min:typ:max, min:typ:max) n(out,in) Only one of Min/Typ/Max values can be used in the entire simulation run It is specified at start of simulation, and depends to the simulator used Typ delay is the default

Delays in Dataflow Modeling Delays in Verilog

Delays in Dataflow Modeling Regular Assignment Delays assign #delay out = in1 & in2; As in Gate-Level Modeling the delay is output-inertial delay

Delays in Dataflow Modeling (cont’d) Implicit Continuous Assignment Delay wire #delay out = in1 & in2;

Delays in Behavioral Modeling Delays in Verilog

Delay in Behavioral Modeling

Today Summary Delays Models Types Delays in Verilog Inertial/Transport Rise/Fall/Turn-off Min/Typ/Max Values Delays in Verilog Gate-Level Modeling Dataflow Modeling Behavioral Modeling

Complementary Notes Assignment 6 Lab. Final Project Chapter 8: All 6 Exercises with ModelSim (submit the Verilog source codes to ce493@ce.sharif.edu) Design appropriate test-benches to exhaustively test the results and report the errors Due date: Saturday, Day 15th Lab. Final Project Announce your group members today Start your work

Complementary Notes (cont’d) Don’t forget to subscribe to course mailing list: ce493list