AT91 Memory Interface This training module describes the External Bus Interface (EBI), which generatesthe signals that control the access to the external memory or peripheral devices.

External Bus Interface (1/2) Features Up to 8 programmable chip select lines Remap Command allows dynamic exception vectors Glue-less for both 8-bit and 16-bit standard memories 16-bit memories emulated with 2 8-bit memories Up to 8 Wait States can be programmed External wait request supported Early Read protocol allows faster clock with slower RAM Data Float Time programming (up to 7) allows connections of high tDF devices The External Bus Interface has 8 chip selects and a 24-bit address bus, the upper four bits of which are multiplexed with chip select lines at the exception of the M55. The remap command enables switching between the boot memory and the internal RAM bank addresses allowing the exception vectors mapped from address 0x0 to 0x20 to be redefined dynamically by the software programs. The 16-bit data bus can be configured to interface with 8-or 16-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing and 2 8-bit data-path memories can be emulated like a 16-bit data-path memory. Up to 8 standard Wait States can be software programmed to access slow peripherals. To insert more Wait States, an external Wait States request may be presented with the assertion of the NWAIT signal. An Early Read protocol has been defined to allow the use of faster clock with slower RAM. A Data Float Time may be programmed to allow connection of devices that free too slowly the data-bus after a read access.

External Bus Interface (2/2) Block Diagram

Byte Access Type Select the most cost effective 16-bit memory implementation Byte Select Access Type : one actual 16-bit memory Byte Write Access Type : 2 8-bit memories Let’s present now the different possible connections with external devices, depending on data-bus path and their control signals. Each chip select with a 16-bit data-path bus can operate with one of two different types of write access. Byte Select Access selects upper and/or lower byte with two byte select lines (NLB and NUB), and separate read and write signals (NRD and NWE). So, it is used to connect 16-bit devices in a memory page and if the device supports byte accesses, NLB enables the lower byte, NUB enables the upper byte. Byte Write Access supports two byte write signals (NWR0 and NWR1) and a single read signal (NRD). So, it is used to connect 2 8-bit devices as a 16-bit memory page. NWR1 enables upper byte writes and NWR0 enables lower byte writes.

Standard RAM connections So, as an example, these are standard RAM connections with: - an 8-bit data-path bus Static RAM: NWR0 drives the Write Enable input, the lower part of the AT91 data-bus is connected to the memory, A0 and A1 to A18 are connected to the memory address signals. - 2 8-bit data-path bus Static RAM used as a single 16-bit data-path device: example of a Byte Write Access Type connection (AT91 evaluation boards situation). - 1 16-bit data-path bus Static RAM with byte access capability: example of a Byte Select Access Type connection.

Standard Flash connections Another example: these are standard Flash connections with: - an 8-bit data-path bus Flash: NWR0 drives the Write Enable input, the lower part of the AT91 data-bus is connected to the memory, A0 and A1 to A18 are connected to the memory address signals. - 2 8-bit data-path bus Flash used as a single 16-bit data-path device: example of a Byte Write Access Type connection. - 1 16-bit data-path bus Flash without byte access capability (this is generally the case), so the Write Enable Flash input is connected to the AT91 NWE signal: in that situation, either Byte Select or Byte Write Access Type software program will work (evaluation boards situation).

The Early Read Protocol Read accesses may be handled with 2 different protocols to take into account peripherals particularities: - Standard read protocol implements a read cycle in which NRD and NWE are similar. Both are active during the second half of the clock cycle. - Early read protocol provides more time for a read access from the memory by asserting NRD at the beginning of the clock cycle. In the case of successive read cycles in the same memory, NRD remains active continuously. So, Early Read protocol can allow a faster clock frequency to be used or work faster by eliminating a Wait State.

Early Read Wait State In Early Read Protocol, the EBI adds automatically one wait state after an external write access to remove any Data Bus contention risks In early read protocol, an early read wait state is automatically inserted when an external write cycle is followed by a read cycle to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is generated in addition to any other programmed wait states (i.e. data float wait). No wait state is added when a read cycle is followed by a write cycle, between consecutive accesses of the same type or between external and internal memory accesses. Early read wait states affect the external bus only. They do not affect internal bus timing.

Standard Programmable Wait States Read Cycle Waveform Write Cycle Waveform About Wait States to access slow peripherals: Each chip select can be programmed to insert one or more (up to 8) wait states during an access on the corresponding device. Note that if NRD is always de-asserted on the MCKI rising edge of the last access cycle, it is not the case for NWR: if standard Wait States are added, NWR is de-asserted one half cycle before the end of the access. Note also the Chip Select Change Wait State: a chip select wait state is added when consecutive accesses are made to 2 different external memories. It is not added if the first access is done with standard wait states.

Calculating required standard wait states with AC Characteristics (1/2) Parameters to be considered tCE = 90ns max tOE = 40ns max So, the requirements are (std read) ntCP - EBI4 - EBI25  tCE ntCP - tCP/2 - EBI22 - EBI25  tOE AT91M55800A EBI Timings @ 32MHz AT49BV1604-90 Read Timings

Calculating required standard wait states with AC Characteristics (2/2) Parameters to be considered: tWP = 100ns min tDS = 100ns min So, the requirements are: (n-1)tCP - EBI8 + EBI10  tWP (n-1)tCP - EBI11 + EBI10  tDS AT91M55800A EBI Timings @ 32MHz AT49BV1604-90 Write Timings

External Wait States To access slow peripherals with more than 8 Wait States NWAIT assertion stops the internal Wait States counter Setup and Hold times to respect, regarding the MCK rising edge So it may be necessary to program one standard Wait State to take into account the decode logic latency

Data Float Time Data Float helps to support devices very slow in releasing the Data Bus Read Device a 2 tdf cycle Read Device b 3 tdf cycle Data Float Time cycles includes internal access cycle Read Device a 2 tdf cycle Internal Access Read Device b 3 tdf cycle Some memory devices are slow to release the external bus. For such devices it is necessary to add wait states (data float waits) after a read access before starting a write access or a read access to a different external memory. It represents the time allowed for the data output to go high impedance after the memory is disabled.

Boot Mode and Remap Command Default Memory 0 configuration : CSR0 = 0x0000203D or 0x0000203E 8 wait states 0 data float time 8/16 bits data bus width selected by BMS if 16 bits data bus width is selected, byte access type is not significant, because continuous read is made in memory 0 Speed up of the boot sequence before remap can be performed by writing EBI_CSR0 Base addresses are defined in EBI registers In EBI_CSR0 for Memory 0 generally corresponds to the link address The ARM vectors are mapped from address 0x0 to address 0x20. The remap command allows these vectors to be redefined dynamically by the software. The remap consists in switching between the boot memory and the internal RAM bank addresses. Before the remap command, the only peripherals accessible are the internal memories and registers and the boot memory, selected by the Chip Select 0, the user can modify the chip select 0 configuration, programming the EBI_CSR0 with the exact boot memory characteristics. The base address becomes effective after the remap command, but the new number of wait states can be changed immediately. This is useful if a boot sequence needs to be faster. The base addresses are defined in the EBI registers, In EBI_CSR0 register for the memory connected to CS0. This base address generally corresponds to the link address.

External Bus Interface Benefits Allows to reach the maximum of performance in Thumb Mode That’s ARM highest performance allowed with a 16-bit bus ! Emulates 2 8-bit memories as a 16-bit one Supports any kind of 8-bit or 16-bit static memory Select the most cost effective memory solution Remap Command maps exception vectors in internal SRAM Fast Interrupt Handling Dynamic Exception Vectors