ECE 434 Advanced Digital System L04 Electrical and Computer Engineering University of Western Ontario

Outline What we know What we do not know Combinational Networks PALs Analysis Synthesis AND-OR-NOTs, NORs, NANDs, MUXes, ROMs, PLAs Hazards in combinational networks What we do not know PALs Sequential Networks Basic Building Blocks Mealy Sequential Networks 17/11/2018 UAH-CPE/EE 422/522 AM

Review: Basic ROM Structure ROM Types Mask-programmable ROM EPROM EEPROM Flash 17/11/2018 UAH-CPE/EE 422/522 AM

Review: Programmable Logic Arrays Perform the same function as a ROM n inputs and m outputs – m functions of n variables AND array – realizes product terms of the input variables OR array – ORs together the product terms 17/11/2018 UAH-CPE/EE 422/522 AM

Review: PLA with 3 inputs, 5 p.t., 4 outputs 17/11/2018 UAH-CPE/EE 422/522 AM

Programmable Array Logic (PALs) PLAs Both AND and OR arrays are programmable PAL is a special case of PLA AND array is programmable and OR array is fixed Motivation for PALs Programmable switches historically presented two difficulties to the manufacturers hard to fabricate correctly => increase the price reduce the speed performance of circuits PALs are less expensive, faster, and easier to program Disadvantage: less flexible 17/11/2018 UAH-CPE/EE 422/522 AM

Programmable Array Logic (PALs) Unprogrammed Programmed 17/11/2018 UAH-CPE/EE 422/522 AM

Using PALs: An Example Implement the following: x x x P P P P 1 2 3 Implement the following: P 1 P 2 P 3 P 4 AND plane 17/11/2018 UAH-CPE/EE 422/522 AM

Using PALs: An Example x x x P f P P f P AND plane 17/11/2018 3 P 1 f 1 P 2 P 3 f 2 P 4 AND plane 17/11/2018 UAH-CPE/EE 422/522 AM

Typical PALs Typical PALs have from 10 to 20 inputs from 2 to 10 outputs from 2 to 8 AND gates driving each OR gate often include D flip-flops f 1 To AND plane D Q Clock Select Enable Flip-flop MUX output is “fed back” to the AND plane. Why? 17/11/2018 UAH-CPE/EE 422/522 AM

Logic Diagram for 16R4 PAL 17/11/2018 UAH-CPE/EE 422/522 AM

Logic Diagram for 16R4 PAL 17/11/2018 UAH-CPE/EE 422/522 AM

Sequential Networks Have memory (state) X = x1 x2... xn Present state depends not only on the current input, but also on all previous inputs (history) Future state depends on the current input and state X = x1 x2... xn Q = Q1 Q2... Qk Z = z1 z2... zm x1 z1 x2 z2 Q Flip-flops are commonly used as storage devices: D-FF, JK-FF, T-FF xn zm 17/11/2018 UAH-CPE/EE 422/522 AM

Clocked D Flip-Flop with Rising-edge Trigger Next state The next state in response to the rising edge of the clock is equal to the D input before the rising edge 17/11/2018 UAH-CPE/EE 422/522 AM

Clocked JK Flip-Flop Next state JK = 00 => no state change occurs JK = 10 => the flip-flop is set to 1, independent of the current state JK = 01 => the flip-flop is always reset to 0 JK = 11 => the flip-flop changes the state Q+ = Q’ 17/11/2018 UAH-CPE/EE 422/522 AM

Clocked JK Flip-Flop Next state T = 1 => the flip-flop changes the state Q+ = Q’ T = 0 => no state change 17/11/2018 UAH-CPE/EE 422/522 AM

S-R Latch 17/11/2018 UAH-CPE/EE 422/522 AM

Transparent D Latch 17/11/2018 UAH-CPE/EE 422/522 AM

Transparent D Latch 17/11/2018 UAH-CPE/EE 422/522 AM

Mealy Sequential Networks General model of Mealy Sequential Network (1) X inputs are changed to a new value After a delay, the Z outputs and next state appear at the output of CM (3) The next state is clocked into the state register and the state changes 17/11/2018 UAH-CPE/EE 422/522 AM

An Example: 8421 BCD to Excess3 BCD Code Converter z Q X (inputs) Z (outputs) t3 t2 t1 t0 1 17/11/2018 UAH-CPE/EE 422/522 AM

State Graph and Table for Code Converter 17/11/2018 UAH-CPE/EE 422/522 AM

State Assignment Rules 17/11/2018 UAH-CPE/EE 422/522 AM

Transition Table 17/11/2018 UAH-CPE/EE 422/522 AM

K-maps 17/11/2018 UAH-CPE/EE 422/522 AM

Realization 17/11/2018 UAH-CPE/EE 422/522 AM

To Do Study textbook chapters Do homework #1 3.1, 3.2, 3.3, 1.6, 1.7 17/11/2018 UAH-CPE/EE 422/522 AM