Presentation Title Stan Williams October 25, 2005 Manufacturability and Computability at the Nano-Scale Frontiers of Extreme Computing This slide/video set is developed in a modular style. It is meant to give Labs personnel basic visuals and videos to pick from when building presentations. The set is an ongoing exercise, so will be updated and added to continually. Objectives are to explain how HP Labs operates within the Hewlett-Packard company and introduce to the audience our leading technologies and areas of interest. Speaker notes are attached on some slides (I will be adding to each visual as time permits) All visuals may be used externally, speaker notes as per your discretion. If you have content information, please contact Glenda Dasmalchi, HPL’s Communications Dept. Palo Alto / 650 857-3786 If you need help with videos, please contact Brett Bausk, HPL’s Communications Dept. Palo Alto / 650 857-7707. Each MPEG video is available for download with a resolution af 320x240. Instructions for inserting videos can be found on the video index page at http://webnt.hpl.hp.com/comms/download/video/index.html Stan Williams October 25, 2005
Discover + Invent "The purpose of QSR is to perform fundamental research in physical science with a strategic intent for hp – to create new technologies that will be important to the company on a 10+ year time frame." Discover + Invent 11/17/2018
Applied Physics A 80, March 2005 “Nanoelectronics” Special Issue For a more detailed discussion of this work, see Applied Physics A 80, March 2005 “Nanoelectronics” Special Issue Journal of Applied Physics 97, #034301 (2005) 2005 WSJ Technology Innovation Award 11/17/2018
Fabrication by Nanoimprint Gun-Young Jung Inkyu Park (Intern) Wei Wu Zhaoning Yu William Tong S.-Y. Wang Hylke Wiersma 11/17/2018
QSR Hyper Moore’s Law Progress 16 k 2005 1 k 2004 64 2003 1 2002 11/17/2018
Lithography Red Brick Wall - 2010 QSR > 13 years ahead! International Technology Roadmap for Semiconductors 2004 year 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 DRAM ½ pitch nm 90 80 70 65 57 50 45 40 35 32 28 25 22 20 30 nm 17 nm 11/17/2018
G4 nanoimprinter: Total cost $300k 10 mm 2nd NIL 1st NIL Wei Wu Much more cost-effective than any commercial nanoimprinter 0.5 mm alignment accuracy demonstrated Targeting 10 nm alignment accuracy (with J. Gao & C. Picciotto) Step & repeat compatible design 11/17/2018
+ Architecture Phil Kuekes Greg Snider Warren Robinett Gadiel Seroussi Ronnie Roth Presentation Title ITR 11/17/2018
Tunneling-Switch Crossbar Circuits US Patents 6128214, 6256767, 6314019 Address lines Memory 1 Switch Data lines Abstraction of a Field-Programmable Gate Array 11/17/2018
Switchable Tunneling Resistor Ti -10 -5 5 10 Current (mA) -2.0 -1.0 0.0 1.0 Voltage (V) Switch on "1" Read bit (measure resistance) Pt Device = Molecule + Electrodes Switch off "0" 11/17/2018
Communicate with the nanowires row selector (demux) memory grid selected column column selected row k-bit address selected memory cell 11/17/2018
Use coding theory to design circuits! Encoder A Y A' Y'A Channel Decoder message codeword corrupted estimate of message Noise k bits n bits U S output Defects Decoder 0 Decoder 1 Decoder 2k-1 Decoder 2k-2 2k bits Protecting messages Protecting calculations? 11/17/2018
Four kbit Cross Bar Memory with Mux/Demux 66x66 cross bar memory @30 nm half-pitch Address lines *Mux/demux propramming done by E-beam burning 11/17/2018
No Gain, No Logic? 11/17/2018
Duncan Stewart TUNNELING SWITCH LATCH: EXPT DATA D Data input Clock / RESET RESTORE ENABLE & INVERT SET 1 SET 2 TUNNELING SWITCH LATCH: EXPT DATA D Data input Clock / control C1 C2 Q out SW1 SW2 E Duncan Stewart 11/17/2018
Expt: Latch works! Signal restoration Inversion, if desired >100mV operating margin No nanoscale transistor! J. Appl. Phys. Feb 1, 2005 11/17/2018
The Tunneling-Switch Latch Provides Logical State Storage Signal Restoration Signal Inversion (Logical NOT) (with no need for a nanoscale transistor) Universal Computation! (Finite State Machine with wired ANDs and ORs) 11/17/2018
Area comparison of NAND gates CMOS NAND gate SIMPL NAND gate Area = 3×(FP)2 = 0.01m2 @ 30 nm hp No VDD, no static power! Low dynamic power Register and Logic Permute inputs and outputs Area = 36×(FP)2 = 1.2m2 @ 90 nm hp 11/17/2018
1 x 17 Latch and Logic Array 11/17/2018
Experimentally measured NAND truth table – Output on Rpull down measured at indicated Step # Output VC Receiving Junction VA VB Driving Junction A Rpull down Driving Junction B Junction A Junction B Rpull down Step # 1 10 19 28 37 11/17/2018
Experimental V vs. t data for NAND demonstration 1 1 1 11/17/2018
Summary of Serial Implication Logic SIMPL is simple! Tunneling switches state machines. Linear array + demux; high density. State encoded with impedance, not voltage. No static power dissipation. Nonvolatile. Conditional copy with inversion is ‘implication’ Compiler construction completed. nanoCircuits built and currently under test. 11/17/2018
Presentation Title 11/17/2018