BARREL SHIFTER.

Slides:

Advertisements

Similar presentations

Introduction To VHDL for Combinational Logic

Advertisements

Chapter 9 Computer Design Basics. 9-2 Datapaths Reminding A digital system (or a simple computer) contains datapath unit and control unit. Datapath: A.

1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.

Quad 2-to-1 and Quad 4-to-1 Multiplexers Discussion D2.4 Example 7.

Decoders Discussion D9.5 Example 25. Decoders 3-to-8 Decoder decoder38.vhd library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all;

1 VLSI DESIGN USING VHDL Part II A workshop by Dr. Junaid Ahmed Zubairi.

Shifters Discussion D7.1 Example Bit Shifter.

Divider Discussion D7.3 Example 20.

Generic Multiplexers: Parameters Discussion D2.5 Example 8.

2-to-1 Multiplexer: if Statement Discussion D2.1 Example 4.

Decoders and Encoders Lecture L4.2. Decoders and Encoders Binary Decoders Binary Encoders Priority Encoders.

Introduction to VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T1: Combinational Logic Circuits.

6/12/20151 Sequence Detectors Lecture Notes – Lab 4 Sequence detection is the act of recognizing a predefined series of inputs A sequence detector is a.

FPGAs and VHDL Lecture L12.1. FPGAs and VHDL Field Programmable Gate Arrays (FPGAs) VHDL –2 x 1 MUX –4 x 1 MUX –An Adder –Binary-to-BCD Converter –A Register.

Chapter 7. Register Transfer and Computer Operations

Introduction to VHDL CSCE 496/896: Embedded Systems Witawas Srisa-an.

4-to-1 Multiplexer: case Statement Discussion D2.3 Example 6.

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448.

Binary-to-BCD Converter

Shift Registers Discussion D5.2 Example Bit Shift Register qs(3) qs(2) qs(1) qs(0) if rising_edge(CLK) then for i in 0 to 2 loop s(i) := s(i+1);

ECE 448: Spring 12 Lab Midterm Exam Review. Part 1: Detailed discussion of a selected midterm from Spring Part 2: Review & discussion of common.

Binary-to-BCD Converter

A.7 Concurrent Assignment Statements Used to assign a value to a signal in an architecture body. Four types of concurrent assignment statements –Simple.

Computer Design Basics

ENG2410 Digital Design LAB #8 LAB #8 Data Path Design.

Shannon decomposition William Sandqvist Claude Shannon mathematician / electrical engineer (1916 –2001) William Sandqvist

VHDL for Combinational Circuits. VHDL We Know Simple assignment statements –f

ECE 332 Digital Electronics and Logic Design Lab Lab 6 Concurrent Statements & Adders.

ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

4-to-1 Multiplexer: Module Instantiation Discussion D2.2 Example 5.

1 Part III: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.

9/9/2006DSD,USIT,GGSIPU1 Concurrent vs Sequential Combinational vs Sequential logic –Combinational logic is that in which the output of the circuit depends.

04/26/20031 ECE 551: Digital System Design & Synthesis Lecture Set : Introduction to VHDL 12.2: VHDL versus Verilog (Separate File)

Lecture 8 Review Combinational Devices –Decoder –Multiplexor (Bhasker p-81) –Shifter –Barrel Shifter (Bhasker p-303)

1 Introduction to Engineering Spring 2007 Lecture 18: Digital Tools 2.

1 Introduction to Engineering Spring 2007 Lecture 19: Digital Tools 3.

16-bit barrel shifter A Mini Project Report

Sequential statements (1) process

Combinational logic circuit

Digital Electronics Multiplexer

Part II A workshop by Dr. Junaid Ahmed Zubairi

Computer Design Basics

Introduction Introduction to VHDL Entities Signals Data & Scalar Types

Hardware Description Languages

Dataflow Style Combinational Design with VHDL

Part IV: VHDL CODING.

Combinational Circuits Using VHDL

Digital Electronics Multiplexer

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

RTL Style در RTL مدار ترتيبي به دو بخش (تركيبي و عناصر حافظه) تقسيم مي شود. مي توان براي هر بخش يك پروسس نوشت يا براي هر دو فقط يك پروسس نوشت. مرتضي صاحب.

Mano and Kime Sections 7-6 – 7-8

ECE 448 Lecture 6 Modeling of Circuits with a Regular Structure Aliases, Constants, Packages Mixing Design Styles ECE 448 – FPGA and ASIC Design with.

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

VHDL (VHSIC Hardware Description Language)

Concurrent vs Sequential

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

Data Flow Description of Combinational-Circuit Building Blocks

Figure 8.1. The general form of a sequential circuit.

UNIT 6: Mixed-Type Description

Computer Design Basics

Data Flow Description of Combinational-Circuit Building Blocks

ECE 448 Lecture 4 Modeling of Circuits with a Regular Structure Constants, Aliases, Packages ECE 448 – FPGA and ASIC Design with VHDL.

Modeling of Circuits with a Regular Structure

ECE 448 Lecture 6 Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code.

ECE 448 Lecture 6 Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL code ECE 448 – FPGA and ASIC Design.

Sequntial-Circuit Building Blocks

Chapter 10 Introduction to VHDL

(Sequential-Circuit Building Blocks)

Presentation transcript:

BARREL SHIFTER

A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. Shifts the input data in combinational manner It can be implemented as a sequence of multiplexers (mux.) or FET A common usage of a barrel shifter is in the hardware implementation of floating-point arithmetic.

PROGRAM library IEEE; use IEEE.STD_1164.all entity BARREL_SHIFTER is Generic (N: POSITIVE:= 4); Port( DATA:in STD_LOGIC_VECTOR(N-1 down to 0)); SELEKT : in INTEGER range 0 to N-1; BARR_OUT : out STD_LOGIC_VECTOR ( N-1 down to 0)); end BARREL_SHIFTER; architechture FOR_LOOP_STYLE of BARREL_SHIFTER is begin process(SELEKT,DATA) variable VAR_BUF: STD_LOGIC_VECTOR( N-1 down to 0)); VAR_BUF:=DATA;

for K in 1 to SELEKT LOOP VAR_BUF := VAR_BUF(N-2 down to 0)& VAR_BUF(N-1); end loop; BARR_OUT<= VAR_BUF; end process; end FOR_LOOP_STYLE; architecture CONCURRENT_STYLE of BARREL_SHIFTER is begin BARRE_OUT<= DATA(N-1- SELEKT down to 0)& DATA(N-1 down to N- SELEKT) When SELEKT> 0; else DATA; end CONCURRENT _STYLE;