Instructor: Alexander Stoytchev CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/

JK Flip-Flops CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © Alexander Stoytchev

Administrative Stuff The FINAL exam is scheduled for Wednesday Dec. 18 @ 7:30-9:30 AM That is 7:30 AM  It will be in this room.

Administrative Stuff Midterm 2 is now graded Check your grade on Blackboard Sample solutions are posted on the class web page If you did not pick up your exam on Wednesday please stop by after class today

Administrative Stuff Extra Credit Homework Posted on the class web page Extra 4% of your grade That is equivalent to extra 20 points on Midterm2 Due on Monday Nov 4 @ 4:00 PM

Quick Review

T Flip-Flop

Motivation A slight modification of the D flip-flop that can be used for some nice applications.

T Flip-Flop [ Figure 5.15a from the textbook ]

Positive-edge-triggered T Flip-Flop Positive-edge-triggered D Flip-Flop [ Figure 5.15a from the textbook ]

T Flip-Flop What is this? [ Figure 5.15a from the textbook ]

What is this? Q T D

What is this? Q T D + = ?

T Flip-Flop T D Q 1 Clock

What is this? Q T D

What is this? Q T D D = QT + QT

What is this? Q T D D = Q + T

What is this? D Q T D = Q + T

What is this? + = ?

T Flip-Flop T D Q Clock

T Flip-Flop (How it Works) If T=0 then it stays in its current state If T=1 then it reverses its current state In other words the circuit “toggles” its state when T=1. This is why it is called T flip-flop.

(circuit and truth table) T Flip-Flop (circuit and truth table) [ Figure 5.15a,b from the textbook ]

(circuit and graphical symbol) T Flip-Flop (circuit and graphical symbol) [ Figure 5.15a,c from the textbook ]

T Flip-Flop (Timing Diagram) [ Figure 5.15d from the textbook ]

JK Flip-Flop

JK Flip-Flop D = JQ + KQ [ Figure 5.16a from the textbook ]

JK Flip-Flop ( ) (b) Truth table (c) Graphical symbol (a) Circuit J Q 1 t + ( ) (b) Truth table (c) Graphical symbol D Clock (a) Circuit [ Figure 5.16 from the textbook ]

JK Flip-Flop (How it Works) A versatile circuit that can be used both as a SR flip-flop and as a T flip flop If J=0 and S =0 it stays in the same state Just like SR It can be set and reset J=S and K=R If J=K=1 then it behaves as a T flip-flop

Registers

Register (Definition) An n-bit structure consisting of flip-flops

Shift Register

A simple shift register D Q Clock In Out t 1 2 3 4 5 6 7 = (b) A sample sequence (a) Circuit [ Figure 5.17 from the textbook ]

Parallel-Access Shift Register

Parallel-access shift register [ Figure 5.18 from the textbook ]

Questions?

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