Digital Logic & Design Dr. Waseem Ikram Lecture No. 34.

Slides:



Advertisements
Similar presentations
©2004 Brooks/Cole FIGURES FOR CHAPTER 12 REGISTERS AND COUNTERS Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter.
Advertisements

Lecture #24 Page 1 EE 367 – Logic Design Lecture #24 Agenda 1.State Machines Review Announcements 1.n/a.
Shift Registers and Shift Register Counters
CS 140L Lecture 7 Professor CK Cheng 11/12/02. Transformation between Mealy and Moore Machines Algorithm: 1) For each NS, z = S i, j create a state S.
EET 1131 Unit 12 Shift Registers
Counters and Registers Wen-Hung Liao, Ph.D.. Objectives Understand several types of schemes used to decode different types of counters. Anticipate and.
Sequential Circuit Introduction to Counter
Registers and Counters
Digital Fundamentals Floyd Chapter 9 Tenth Edition
Figure 9–1 The flip-flop as a storage element.
Chapter 8 -- Analysis and Synthesis of Synchronous Sequential Circuits.
Digital Design Lectures 11 & 12 Shift Registers and Counters.
Counters and Registers
Digital Electronics Electronics Technology Landon Johnson Shift Registers.
Digital Fundamentals Tenth Edition Floyd Chapter 9.
A sequential logic circuit (a.k.a. state machine) consists of both combinational logic circuit(s) and memory devices (flip flops). The combinational circuits.
DIGITAL SYSTEMS TCE Shift Registers and Shift Register Counters Week 10 and Week 11 (Lecture 2 of 2)
Counters and registers Eng.Maha Alqubali. Registers Registers are groups of flip-flops, where each flip- flop is capable of storing one bit of information.
Lecture No. 29 Sequential Logic.
Logic Design (CE1111 ) Lecture 6 (Chapter 6) Registers &Counters Prepared by Dr. Lamiaa Elshenawy 1.
Digital Logic & Design Dr. Waseem Ikram Lecture No. 26.
CSE 260 Digital Logic Design Registers, Memory BRAC University.
REGISTERS - Introduction to Registers Shift Registers Lecture 1 Gunjeet Kaur Dronacharya Group of Institutions.
Digital Logic & Design Dr. Waseem Ikram Lecture No. 35.
Shift Register Counters
Digital Logic & Design Dr. Waseem Ikram Lecture No. 25.
Partitioning of a digital system.
EET 1131 Unit 12 Shift Registers
Figure 8.1. The general form of a sequential circuit.
Electronics Technology
Introduction to Advanced Digital Design (14 Marks)
Digital Fundamentals Abdul Hameed
Serial In/Parallel Out Shift Registers
EKT 124 / 3 DIGITAL ELEKTRONIC 1
Digital Logic & Design Dr. Waseem Ikram Lecture No. 28.
EEL 3705 / 3705L Digital Logic Design
Sequential Logic Counters and Registers
Figure 12-13: Synchronous Binary Counter
FIGURE 5.1 Block diagram of sequential circuit
Sequential Circuit: Counter
Digital Design Lecture 9
Counters and Registers
CHAPTER 9 Shift Registers
Dr. Clincy Professor of CS
Digital Logic & Design Dr. Waseem Ikram Lecture No. 30.
Malik Najmus Siraj Digital Logic Design Malik Najmus Siraj
Digital Principles and Design Algorithmic State Machines
Digital System Design Review.
Digital Logic & Design Dr. Waseem Ikram Lecture 38.
EET 1131 Unit 12 Shift Registers
ECE 3130 – Digital Electronics and Design
Lecture No. 24 Sequential Logic.
Recap D flip-flop based counter Flip-flop transition table
Digital Logic & Design Dr. Waseem Ikram Lecture No. 31.
Digital Logic & Design Dr. Waseem Ikram Lecture No. 16.
CSE 370 – Winter Sequential Logic-2 - 1
ECE 3130 – Digital Electronics and Design
Lecture 17 Logistics Last lecture Today HW5 due on Wednesday
Lecture No. 32 Sequential Logic.
Digital Logic & Design Dr. Waseem Ikram Lecture No. 36.
Switching Theory and Logic Design Chapter 5:
Digital Logic Department of CNET Chapter-6
Digital Logic Department of CNET Chapter-6
SYEN 3330 Digital Systems Chapter 6 – Part 3 SYEN 3330 Digital Systems.
14 Digital Systems.
Lecture 17 Logistics Last lecture Today HW5 due on Wednesday
Instructor: Alexander Stoytchev
Reference Chapter 7 Moris Mano 4th Edition
Serial In/Parallel Out Shift Registers
Shift Registers Dr. Rebhi S. Baraka
Presentation transcript:

Digital Logic & Design Dr. Waseem Ikram Lecture No. 34

Recap State Assignment Flip-flop input table & K map for 1st assignment

Recap Moore Machine State Diagram Next-State Table J-K flip-flop Input Table Karnaugh Maps Implementation Timing diagram

Recap Mealy Machine State Diagram Next-State Table State Assignment J-K flip-flop Input Table Karnaugh Maps Implementation Timing diagram Output

Serial In/Serial Right/Serial Out Operation

Serial In/Serial Left/Serial Out Operation

Serial In/Shift Right/Serial Out Register

Timing diagram of a Serial In/Shift Right/Serial Out Register

Bi-directional, 4-bit Shift register

Timing diagram of a Bi-directional, 4-bit Shift register

Serial In/Parallel Out Operation

74HC164, 8-bit Serial In/Parallel Out Shift Register

Timing diagram of a 74HC164, 8-bit Serial In/Parallel Out Shift Register

Parallel In/Serial Out Operation

4-bit Parallel In/Serial Out Shift register

74HC165, 8-bit Parallel In/Serial Out Shift Register

Parallel In/Parallel Out Operation

A D-flip-flop based 4-bit Parallel In/Parallel Out Register

74HC195, 4-bit Parallel In/Parallel Out Shift Register

Rotate Right Operation

Rotate Left Operation

4-bit Johnson Counter

Sequence of states of a 4-bit Johnson Counter Clock Pulse Q0 Q1 Q2 Q3 1 2 3 4 5 6 7

4-bit Ring Counter

Sequence of states of a 4-bit Ring Counter Clock Pulse Q0 Q1 Q2 Q3 1 2 3

Shift Registers Serial In/Shift Right/Serial Out (fig 1) Serial In/Shift Left/Serial Out (fig 2) D flip-flop based Serial Shift Reg. (fig 3a) Timing diagram (fig 3b) Universal Serial register (fig 4a) Timing diagram (fig 4b)

Shift Registers Serial In/Parallel Out (fig 5) Serial In/Parallel Out 74HC164 (fig 6a) Timing diagram (fig 6b) Parallel In/Serial Out (fig 7) Circuit diagram Parallel In/Serial Out (fig 8) 74HC165 (fig 9)

Shift Registers Parallel In/Parallel Out (fig 10) Parallel In/Parallel Out circuit (fig 11) 74HC195 (fig 12) 74HC194 (fig 13) Universal Shift reg.

Rotate Operations Rotate Right Operation (fig 14) Rotate Left Operation (fig 15) Johnson Counter (fig 16, tab 1) Ring Counter (fig 17, tab 2)