Digital Logic & Design Dr. Waseem Ikram Lecture No. 34
Recap State Assignment Flip-flop input table & K map for 1st assignment
Recap Moore Machine State Diagram Next-State Table J-K flip-flop Input Table Karnaugh Maps Implementation Timing diagram
Recap Mealy Machine State Diagram Next-State Table State Assignment J-K flip-flop Input Table Karnaugh Maps Implementation Timing diagram Output
Serial In/Serial Right/Serial Out Operation
Serial In/Serial Left/Serial Out Operation
Serial In/Shift Right/Serial Out Register
Timing diagram of a Serial In/Shift Right/Serial Out Register
Bi-directional, 4-bit Shift register
Timing diagram of a Bi-directional, 4-bit Shift register
Serial In/Parallel Out Operation
74HC164, 8-bit Serial In/Parallel Out Shift Register
Timing diagram of a 74HC164, 8-bit Serial In/Parallel Out Shift Register
Parallel In/Serial Out Operation
4-bit Parallel In/Serial Out Shift register
74HC165, 8-bit Parallel In/Serial Out Shift Register
Parallel In/Parallel Out Operation
A D-flip-flop based 4-bit Parallel In/Parallel Out Register
74HC195, 4-bit Parallel In/Parallel Out Shift Register
Rotate Right Operation
Rotate Left Operation
4-bit Johnson Counter
Sequence of states of a 4-bit Johnson Counter Clock Pulse Q0 Q1 Q2 Q3 1 2 3 4 5 6 7
4-bit Ring Counter
Sequence of states of a 4-bit Ring Counter Clock Pulse Q0 Q1 Q2 Q3 1 2 3
Shift Registers Serial In/Shift Right/Serial Out (fig 1) Serial In/Shift Left/Serial Out (fig 2) D flip-flop based Serial Shift Reg. (fig 3a) Timing diagram (fig 3b) Universal Serial register (fig 4a) Timing diagram (fig 4b)
Shift Registers Serial In/Parallel Out (fig 5) Serial In/Parallel Out 74HC164 (fig 6a) Timing diagram (fig 6b) Parallel In/Serial Out (fig 7) Circuit diagram Parallel In/Serial Out (fig 8) 74HC165 (fig 9)
Shift Registers Parallel In/Parallel Out (fig 10) Parallel In/Parallel Out circuit (fig 11) 74HC195 (fig 12) 74HC194 (fig 13) Universal Shift reg.
Rotate Operations Rotate Right Operation (fig 14) Rotate Left Operation (fig 15) Johnson Counter (fig 16, tab 1) Ring Counter (fig 17, tab 2)