Fast, Asynchronous SRAM

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Presentation transcript:

Fast, Asynchronous SRAM Lecture L9.1

buff3.vhd en input output library IEEE; use IEEE.STD_LOGIC_1164.all; entity buff3 is generic (width:positive); port( input : in STD_LOGIC_vector(width-1 downto 0); en : in STD_LOGIC; output : out STD_LOGIC_vector(width-1 downto 0) ); end buff3; architecture buff3 of buff3 is begin output <= input when en = '1' else (others => 'Z'); input output

RAM Module

WHYP words to read and write data to memory ! ( data addr -- ) \ “store” data at addr @ ( addr – data ) \ “fetch” data from addr

! ( data addr -- ) \ “store” data at addr when store => cs <= '0'; oe <= '1'; pinc <= '0'; if ccycle = 1 then we <= '0'; else tload <= '1'; nload <= '1'; tsel <= "111"; nsel <= "01"; dpop <= '1'; end if;

Add to wc16_control MultiCC: process (clk, clr, current_state) begin if clr = '1' then ccycle <= "000001"; elsif (clk'event and clk = '1') then if current_state = exec then ccycle <= ccycle + 1; else end if; end process MultiCC;

In wc16_control add…. Store (!) when exec => -- execute instr without fetching next one if (icode = X"010E" or icode = X"010F") and ccycle < 3 then next_state <= exec; elsif (icode = X"0110" or icode = X"0111") and ccycle < 8 then --elsif icode = X"Code_for_multi-cycle" -- and ccycle < Num_cc_to_exec then -- next_state <= exec; else next_state <= fetch; -- go to fetch state end if;

@ ( addr – data ) \ “fetch” data from addr when RAMfetch => -- read RAM in E1 tload <= '1'; tsel <= "100"; cs <= '0'; oe <= '0';

\ Test of ram @ and ! HEX : main ( -- ) 1234 5 BEGIN waitB0 OVER OVER ! DUP @ DIG! SWAP 1+ SWAP 1+ AGAIN ;

\ Test of ram @ and ! HEX : main ( -- ) 1234 5 BEGIN waitB0 JMP, --0 X"0002", --1 LIT, --2 X"1234", --3 LIT, --4 X"0005", --5 JB0HI, --6 X"0006", --7 JB0LO, --8 X"0008", --9 over, --a over, --b store, --c dup, --d RAMfetch, --e digstore, --f swap, --10 plus1, --11 swap, --12 plus1, --13 JMP, --14 X"0006", --15 X"0000" --16 \ Test of ram @ and ! HEX : main ( -- ) 1234 5 BEGIN waitB0 OVER OVER ! DUP @ DIG! SWAP 1+ SWAP 1+ AGAIN ;