Organizers Adwait Jog Assistant Professor (William & Mary)

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Presentation transcript:

Min-Move 2018 2nd Workshop on Hardware/Software Techniques for Minimizing Data Movement

Organizers Adwait Jog Assistant Professor (William & Mary) Computer Architecture, GPUs www.cs.wm.edu/~adwait Also local arrangements co-chair for ASPLOS EJ Kim Associate Professor, Texas A&M University Computer Architecture, Interconnects, Performance Evaluation http://faculty.cse.tamu.edu/ejkim/

Scope Any idea/technique that can help in reducing the data movement is appropriate for this workshop. Some topics (but not limited to) are: Near Data Processing (e.g., near caches or memory or storage devices) In-Memory Computing (e.g., in caches or memory or storage devices) Approximate Computing (e.g., load value approximations) Cache/DRAM Locality Optimizations Data Compression Techniques Emerging Memory Technologies (e.g., STT-RAM, Memristor) Non Von-Neumann Architectures (e.g., Quantum Architectures, Automata Processor) Interconnection Architectures (e.g., on-chip, off-chip, Ethernet, interposer system, flexible interconnects for FPGA) Programming and Language Support for Minimizing Data Movement

Program Committee Niladrish Chatterjee (Nvidia) Reetuparna Das (UMich) Myoungsoo Jung (Yonsei) David Kaeli (Northeastern) Onur Kayiran (AMD Research) Aasheesh Kolli (VMWare and Penn State) Asit Mishra (Intel) Yoonho Park (IBM) Gennady Pekhimenko (UToronto) Lawrence Rauchwerger (Texas A&M)

Highlights of the Workshop Keynotes from Rajeev Balasubramonian (Utah) Reetuparna Das (Michigan) Alessandro Morari (IBM) Peer-Reviewed Workshop Paper (received three reviews) An Extensible Scheduler for the OpenLambda FaaS Platform Authors: Gustavo Totoy, Edwin Boza, and Cristina Abad (ESPOL, Eucador)