Cache-Efficient Layouts of BVHs and Meshes 2 Sung-Eui Yoon, Peter Lindstrom, Dinesh Manocha 1: Lawrence Livermore National Laboratory 2: University of North Carolina - Chapel Hill 1 1 http://gamma.cs.unc.edu/COL/OpenCCL/ Abstract: Current computer architectures employ various caches to improve the performance of a wide variety of applications. One of the main characteristics of such cache schemes is the use of block fetching whenever an uncached data element is accessed. To maximize its benefits, we present novel cache-efficient layouts of polygonal meshes and bounding volume hierarchies that improve the performance of interactive visualization and geometric processing algorithms. By using our cache-efficient layouts, we are able to improve the performance of various applications without any code modifications. Source codes of our work are available as the OpenCCL library. Our Goals: Theoretical Results: – Derive a metric measuring the expected number of cache misses of layouts given an I/O model – Measure the probability that a bounding volume node of BVHs will be accessed at runtime – Design efficient layout algorithms for meshes and hierarchies given metrics – Computing cache-aware layouts of graphs representing runtime access patterns is reduced to graph partitioning – Cache-oblivious metrics predicting the number of cache misses are either a linear or a log function of edge lengths in the layout depending on a block size assumption – New probabilistic model predicting runtime behavior on BVHs 105 Cache: Block: Memory: Two level I/O Model Optimized layouts with our metrics Results on Meshes: Results on BVHs: Below left, we test different layouts during iso-surface extraction from the Spx tetrahedral mesh (140K vertices). Below right, GPU vertex cache miss ratios are shown during view-dependent rendering of the power plant model (12M triangles) Power plant with Hugo robot model Collision detection time between the power plant and robot models Collision detection times Render time of ray tracing of Lucy model Comparison with other layouts in Iso-Surface Extraction GPU vertex cache miss ratio of different layouts This work was performed under the auspices of the U.S. Department of Energy by University of California Lawrence Livermore National Laboratory under contract No. W-7405-Eng-48. UCRL-POST-221342