CSE 140: Discussion #4 Nima Mousavi

Content Questions about midterm Encoder/Decoder Multiplexers Adder/Subtractor ALU

Any questions about midterm?

Decoder Review Why do we use decoder? Dont forget to label your decoders!! (enumerating the inputs/outputs) A decoder implements all the minterm, so if we have the SOP canonical of a function we can easily implement that with an OR gate and the decoder.

Decoder Review If En = 1, I0 = 0 , I1=1 and I2 = 0, which of the outputs is one? If En = 1, I0 = 0 , I1=1 and I2 =1, which of the outputs is one? If En = 0, I0 = 1 , I1=0 and I2 =1, which of the outputs is one?

Implementing with 4:16 Decoder & OR gates Starting from Canonical SOP forms Y1 = ∑m(3,5,6,7,9) + D(10,11,12,13,14,15) Y0 = ∑m(1,2,4,7,8) + D(10,11,12,13,14,15)

Implementing with 4:16 Decoder & OR gates Y1 = ∑m(3,5,6,7,9) + D(10,11,12,13,14,15) Y0 = ∑m(1,2,4,7,8) + D(10,11,12,13,14,15) I3:msb We can use one decoder to implement multiple outputs No need for logic minimization Some outputs can be left unused We can reuse the ouputs Y1 a3 I3 I2 I1 I0 a2 a1 a0 Y0 What about the dont cares?

Implementing with 4:16 Decoder & OR gates I3:msb LABELS!! Y1 a3 I3 I2 I1 I0 a2 a1 a0 Y0

Tree of decoders Implementing a function with n inputs using n to 2^n decoder is straightforward, but can we use smaller decoders? We need to know how to build big decoders from smaller ones. 4:16 decoder from 3:8 ones. 4:16 decoder from 2:4 ones ….

4:16 decoders form 3:8 ones 1 ? ? a2 a1 a0 ? I2: msb a3 ? ? a2 a1 a0 ?

4:16 decoders form 3:8 ones The OR gates will not change a3’ a3’a2’a1’a0’ a3’a2’a1’a0 a2 I2 I1 I0 a1 a0 y3 y5 Y1 y6 a3’a2a1a0 y7 y9 I2: msb a3 a3a2’a1’a0’ a3a2’a1’a0 a2 I2 I1 I0 y1 a1 y2 Y0 a0 y4 y7 y8 a3a2a1a0

4:16 decoders form 2:4 ones

Multiplexer Based on the value of the selectors, one of the inputs are selected and connected to the output. One output N selectors 2^N inputs

Example If (X0,X1,X2,X3)= (1,0,1,0) and (S1,S0)=(1,0) then Y = ? If (X0,X1,X2,X3)= (1,0,1,0) and (S1,S0)=(0,1) then Y = ? If (X0,X1,X2,X3)= (1,0,1,0) and (S1,S0)=(1,1) then Y = ? 1 1 S1 is the msb

Example What is function Y? Y = ? 1 a a’ 1 b c

Example What is function Y? 1 Y = b’c’ + b’c + bc’ + bc If b=0 and c =0 , X0 will be selected which is equal to a. So a will appear at the output y only if b’c’ is true -> ab’c’ 1 a a’ 1 b c

Example What is function Y? 1 Y = a b’c’ + a’ b’c + 1 bc’ + 0 bc b c

Example 1 1 d y1 1 f a’ 1 d’ y2 b c What is function f? We need to find y1 and y2. 1 d 1 1 y1 f a’ ? ? ? ? 1 d’ y2 b c

Example y1 = a’ + a ? ? 1 d 1 y1 1 f a’ 1 d’ y2 b c

Example d 1 1 d 1 1 y1 ? ? f a’ 1 d’ y2 b c y1 = a’ + a = da’ + a 1 d’ y2 b c

Example d 1 1 1 d y1 1 f a’ 1 d’ y2 b c y1 = a’ + a = da’ + a y2= a’ + a = a’d’ Now we can get the expression for f. d 1 1 d 1 1 y1 d’ f a’ 1 d’ y2 b c

Example 1 1 d y1 1 f a’ 1 d’ y2 b c y1 = da’ + a y2= a’d’ f= b’c’+ b’c + bc’ + bc 1 d 1 1 y1 f a’ 1 d’ y2 b c

Example y1 = da’ + a 1 y2= a’d’ f= b’c’+ b’c + bc’ + bc 1 d = (da’+a) b’c’ + a’b’c + a’d’bc 1 d 1 1 y1 y1 a’ y2 f a’ 1 d’ y2 b c

Implement with 8:1 mux S2 is msb a b c Y 1 x 1 a=0,b=0,c=0 1 1 x 1 a=0,b=0,c=0 1 a=0,b=0,c=1 a=0,b=1,c=0

Implement with 4:1 mux a b c Y 1 x 1 ?

Implement with 4:1 mux a b c Y 1 x c ?

Implement with 4:1 mux a b c Y 1 x 1 c ?

Implement with 4:1 mux a b c Y 1 x 1 c 1 ?

Implement with 4:1 mux a b c Y 1 x 1 c 1 c’

Implement with 2:1 muxes a b c Y 1 x If a = 0, then D(b=0,c=0) =0 1 x If a = 0, then D(b=0,c=0) =0 D(b=0,c=1) =1 D(b=1,c=0) =0 D(b=1,c=1) =0 1 D? We define another function D in which “a” is constant. D depends on b,c. We want to find the expression for D!

Implement with 2:1 muxes a b c Y 1 x If a = 0, then D(b=0,c=0) =0 1 x If a = 0, then D(b=0,c=0) =0 D(b=0,c=1) =1 D(b=1,c=0) =0 D(b=1,c=1) =0 1 D b\c c=0 c=1 b=0 1 b=1 But we dont have an AND gate! D=b’c

Implement with 2:1 muxes 1 D=b’c D(b=0, c) =c D(b=1, c) =0 c a b c Y 1 1 x b’c 1 b This mux implements b’c. b’c + 0b = b’c

Implement with 2:1 muxes 1 c a b c Y 1 x b’c 1 b H? If a = 0, then 1 x b’c 1 b H? If a = 0, then H(b=0,c=0) =1 H(b=0,c=1) =X H(b=1,c=0) =1 H(b=1,c=1) =0 b\c c=0 c=1 b=0 1 X b=1 H=c’

Implement with 2:1 muxes 1 c a b c Y 1 x b’c 1 b c’ If a = 0, then 1 x b’c 1 b c’ If a = 0, then H(b=0,c=0) =1 H(b=0,c=1) =X H(b=1,c=0) =1 H(b=1,c=1) =0 b\c c=0 c=1 b=0 1 X b=1 H=c’

Implement with 2:1 muxes 1 c a b c Y 1 x b’c 1 b c’

Half Adder A B S C 1

Full Adder A B Cin S Co 1

Ripple Carry Adder Disadvantage: Slow Similar to last slide, you can replace FA with 2 HA, logic gates, etc.

ALU Design ALU with two 4 bit inputs A, B and 2 control inputs X, Z. X Y Operation A 1 -A A xor B A nand B

Design Circuit for A and -A F = A when Z = 0 F = -A when Z=1 ( -A is 2’s complement of A)

ALU Design