Achieving Best QoR and Fastest TAT with Synopsys Fusion Technology Dr. Thomas Andersen, Senior Director, Engineering, Synopsys Design Group May 1, 2018 May 1, 2018

Synopsys Fusion Technology Best QoR and Fastest TTR Fusion Data Model PT, StarRC, PTPX, ICV, RedHawk Synthesis IC Compiler II Test Design Fusion ECO Fusion Signoff Fusion Test Fusion Technology Leadership #1 Anchors: Synthesis, P&R, STA, Extraction Massively Parallel New Fusion Architecture Best QoR: Tech Moves Across Products Fastest TTR: Common Platform Engines 4 Fusion Types: Design, ECO, Signoff & Test New Digital Intelligence Machine Learning Throughout Additional QoR, TTR May 1, 2018

Design Fusion Common Technology Between Synthesis and P&R Test Fusion Signoff Fusion ECO Fusion Enables Convergence, Fastest TTR e.g. Congestion . Synthesis P&R Synthesis Technology moves inside P&R for Best QoR Synthesis QoR inside P&R P&R QoR inside Synthesis Unified Optimization Strategy In addition, we are working on ‘Flexible Handoff’ from synt to P&R. This allows the front-end designers to go deeper into physical design – from netlist level all the way to legalized placement. Handoff can be of netlist, pre-legalized placement or legalized placement. May 1, 2018

Design Fusion Results Synthesis based Logic Optimization inside P&R Improved QoR, flexible handoff and faster convergence Customer Results Up to 5% Area reduction Up to 10% Leakage reduction Significant Congestion Reduction          May 1, 2018

ECO Fusion 30% Reduction in ECO TTR & Better QoR Exiting P&R Test Fusion Signoff Fusion Design Fusion route_opt with PT & StarRC ECO Fusion IC Compiler II PrimeTime & StarRC PBA (Path Based Analysis) Optimization in P&R for Best QoR 30% Reduction in ECO TTR Better QoR from P&R Flow May 1, 2018

4 Manual ECOs Iterations ECO Fusion ECO Fusion Convergence with Implementation Scenarios Accelerates Sign-off Closure ICC2 PT&ICC2 PT route_opt 4 Manual ECOs Iterations ICC2 PT 30% Faster ECO Fusion Reduced route_opt May 1, 2018

Signoff Fusion PrimeTime, StarRC, PT-PX & RedHawk for Optimization AND Signoff Test Fusion Design Fusion ECO Fusion Golden Sign-off Analysis in Optimization Zero Margin Platform Eliminates Pessimism With Signoff fusion, we are using PT and StarRC for signoff and for optimization across the flow. Industry golden signoff tech will be fused with implementation. The timing and analysis engines will be brought to synthesis and P&R. This enables perfect correlation. As a result, the platform becomes zero margin enabled. We are going to extend the backbone to IR and Thermal as well. Exclusive RedHawk Fusion Extends to IR, Thermal May 1, 2018

Signoff Fusion Exclusive Partnership with Ansys CALL TO ACTION Traditional Signoff Fusion IC Compiler II IC Compiler II RedHawk Fusion 237 mV worst IR drop StarRC StarRC PT / PT PX PT / PT PX 196 mV worst IR drop RedHawk Manual Iterative Automated Clean Block Handoff Excellent Correlation and Results May 1, 2018

Synopsys Fusion Technology Best QoR and Fastest TTR Fusion Data Model PT, StarRC, PTPX, ICV, RedHawk Synthesis IC Compiler II Test Design Fusion ECO Fusion Signoff Fusion Test Fusion Technology Leadership #1 Anchors: Synthesis, P&R, STA, Extraction Massively Parallel New Fusion Architecture 10% Better QoR: Tech Moves Across Products 2X Faster TTR: Common Platform Engines 4 Fusion Types: Design, ECO, Signoff & Test New Digital Intelligence Machine Learning Throughout Additional QoR, TTR, Productivity May 1, 2018

The Rise of Machine-Learning Enabling new applications across almost all aspects of the global economy May 1, 2018

Machine-Learning for EDA: Why? A quick look at current semiconductor and design economics Cost Complexity Design INTEL, TECHNOLOGY & MANUFACTURING DAY, 2017 ARXIV:1402.2459V1 [CS.AR] 11 FEB 2014 NVIDIA, SNUG SILICON VALLEY 2018 Moore’s Law has slowed down Designing ICs is expensive (7nm: >$250M [Gartner]) New node ROI: No less than perfect required Most problems are intractable Competing heuristics, iterations, chaos Agony of choice: what to do next? EDA solutions deterministic in nature High-automation, high-configurability Paradox Many, many moving parts in EDA flows Promise of Machine-Learning in EDA: Make our Design World SIMPLER May 1, 2018

Synopsys’ Approach to Machine-Learning Initiatives Bringing “Digital Intelligence” to the Design Platform BETTER QOR, FASTER TTR ML-Enhanced Engines “NO-HUMAN-IN-THE-LOOP” PRODUCTIVITY New, ML-Driven Applications Power Optimization Flow ML Apps Tool/Flow Parameters Route Prediction Debug ML Apps Failure Prediction High-Σ Simulation Design ML Apps Exploration DRC Scheduling S/W Quality ML Apps Release, regression, triage May 1, 2018

Machine Learning: PT ECO Power Recovery Machine Learning for ECO Optimization Training High power circuits Low power circuits Equivalent 2018 Target 5X Training DB User generated/owned Design style specific Prediction Optimize power? 5-10X Faster Target 3-5X speedup by 2018 production May 1, 2018

New, ML-Driven Applications Addressing moving parts and manual steps in the broader design environment Tool and Flow Settings (max_util, placement bounds, ICG) Design Collateral (PVT selection, layer stack, track height) Foundry / Process (DRC, stack variability, DFM, patterning) Hierarchy (Floorplan, macro placement, IP integration) 2017 Study: High-Performance ARM Core Implementation Question: Which is the best setting for channel blockage density? May 1, 2018

Automatically Optimized multiple parameters concurrently Arm Next Generation Core Example Better QoR and Productivity with Machine Learning Full-flow Within the Tools 7nm Arm NextGen Core 3.5 GHz Compute Envelope Syn params Baseline, ARM NextGen Reference Flow, 4 engineers over 7 months Synthesis Calendar Envelope P&R params 1 engineer 3 days Placement 100 MHz higher FMAX 60% TNS reduction 3% congestion reduction Automatically Optimized multiple parameters concurrently May 1, 2018

The Road to Digital Intelligence Goal: Make Design SIMPLER More Predictive Models More Predictive Flows Design Assistance Design Process Automation Power optimization Routability & SI Layer assignment Memory & runtime Tool/flow parameters “Doomed” runs MCMM impact QoR evolution Risk assessment Anomaly detection Debug assistance Natural language Floorplan assessment Constraints, blockages Resource optimization Enterprise-level planning Predict tool outcomes Accelerate closure Predict flow outcomes Simplify decisions Influence outcomes Minimize risk Prescribe outcomes “No-human-in-the-loop” May 1, 2018

Summary May 1, 2018 Market and Design Leadership #1 market and segment leadership: Computing, Mobile, AI, Automotive and Memory Enabling 92% of 10/8/7nm designs and 6X more tapeouts exclusively with Synopsys Bold vision redefines Chip Design Systematic execution of our Fusion Technology Strategy redefines design Our exclusive Ansys partnership is benefiting all customers Innovation across DG products is leading the industry and enabling our customers Strong Investment in Machine Learning Machine-learning has emerged as a powerful technology for addressing high-complexity, high-cost challenges Synopsys is investing in ML-based solutions across the digital platform ML enhancements within the platform with impressive early results Entire new applications around the platform May 1, 2018

May 1, 2018