Willy Sedano, Graduate Student - University of Wisconsin-Milwaukee

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Presentation transcript:

Medium Voltage Architecture for Microgrids and Shipboards by Comparing Devices and Architectures Willy Sedano, Graduate Student - University of Wisconsin-Milwaukee Robert Cuzner, Assistant Professor - University of Wisconsin-Milwaukee

Introduction Determine Size/Weight of Architectures. Assess their Survivability and Reliability of Power (Quality of Service). Approximately 20kVdc system is assumed (based upon 13.8kVac generator feeds). Emphasis on line-to-line and line-to-ground short circuit fault protective strategy. Look at Solid State Protective Device (SSPD) topologies. Consider capabilities and improvements enabled by the use of wide bandgap power semiconductors (specifically SiC MOSFET, IGBT and SGTO). Include Solid State Transformer (SST) interfaces between MVDC and Low Voltage (LV) system.

Importance of this research Using the emerging technology of the Wide Bang Gap devices to handle higher current and allow for better capability for most of the MVDC architectures. This will allow us to reach the MV for electric shipboards and microgrids. Find the optimal architecture for MVDC systems, base on size weight, survivability and reliability. Low cost simulation, validation an implementation by using Opal-RT and Typhoon-HiL as our hardware in the loop. Investigate EMI properties for MVDC switching converters.

Breaker and Breaker less system An Integrated Power System needs to have a protective strategy that simultaneously meets the goals of an efficient, survivable and cost effective architecture. This study emphasizes that the fault protective strategy is the backbone for the negative line-to-ground fault in the Integrated Power Systems because it drives the peak current ratings of power conversion and protective equipment. In power electronics systems, the peak current ratings have the most direct impact on the equipment size and weight. In order to limit the rate of rise of current (di/dt), inductors must be sized so that they do not saturate when a fault occurs.

10kV SiC MOSFET Dual Ring Bus (“Breaker-Based”) High Reliability of Power High Cost CSC Based PGM (“Breaker-Less”) Low Reliability of Power Low Cost