Current Source & Bias Circuits CSE598A/EE597G Spring 2006 Current Source & Bias Circuits Insoo Kim, Kyusun Choi Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Pennsylvania State University

Introduction Required Features of Current Source High Rout Wide Operation Range Constant Current Source Low PVT (Process, Voltage, Temperature) Sensitivity Required Features of Bias Circuit Low Rout Low PVT Sensitivity 11/19/2018

Basic Current Source Wilson Current Mirror Cascode Current Mirror

Ideal vs. Actual Current Source 11/19/2018 Ideal vs. Actual Current Source 11/19/2018

Simple NMOS Current Source What’s the bad feature of this? 11/19/2018

Cascode Current Source What’s the bad feature of this? 11/19/2018

Basic Current Mirror What’s the bad feature of this? 11/19/2018

Wilson Current Mirror What’s the drawback of this circuit? 11/19/2018

Cascode Current Mirror But, it still has limited output swing problem. 11/19/2018

Wide Swing Cascode Current Mirror 11/19/2018

Self Bias Circuits PTAT Bias Circuits Band gap Reference

Power Supply Dependency of Current Source Consideration Factors - VDD - Channel Length Modulation - Transistor Mismatch How do we generate Iref independent of the supply voltage? 11/19/2018

Self Biasing Circuit What’s role of Rs? What’s the advantage of these circuits? What’s the problem of these circuits? 11/19/2018

Improved Self Biasing Circuit Improved Circuit with Start-up Circuit * This Circuit is practical only if Improved Circuit eliminating Body Effect 11/19/2018

A Simple Temperature Compensation Concept M1(Vgs) M1(Ids) 0℃ 90℃ ZTC (Zero Temperature Coefficient) Negative TC Positive TC VDD VDD vr0 v M1 R1 1. R1 is a conductor which has positive TC 2. M1 has negative TC below ZTC point (Semiconductor) 3. If we control Vr0 below ZTC point, Vr0 become less sensitive to temperature due to opposite TC of M1 and R1 Self Bias Circuit 11/19/2018

Case Study (I) – Self Bias Circuit in DRAM ⓐ ⓑ starter For Temp. Compensation pmos diode vref Vext What’s the drawback of these circuits? 11/19/2018

Case Study (II) – Self Bias Circuit in DRAM Why does this circuit need the voltage buffer? Why are PMOS current mirrors stacked in the reference bias circuit? ⓐ vr1 ⓐ Voltage Buffer starter For Temp. Compensation 11/19/2018

VBE Referenced CMOS Self-bias Circuit How do we fabricate BJT in CMOS Process Technology? * Temperature Sensitivity ~ - 4000 ppm/C 11/19/2018

Realization of pnp BJT in CMOS Technology 11/19/2018

Vth Referenced CMOS Self-Bias Circuit 11/19/2018

Thermal Voltage Referenced CMOS Self-Bias Circuit 11/19/2018

Thermal Voltage Referenced CMOS Self-Bias Circuit * Temp. Sensitivity ~ +3300 ppm/C 11/19/2018

CMOS Band gap Reference What’s the problem? 11/19/2018

(cont’d) CMOS Band gap Reference Actual Implementation of CMOS Band Gap Reference 11/19/2018

Actual Implementation of CMOS Band gap Reference 11/19/2018

Design Lab. – Self Bias Circuit with Temp. Compensation Schematics * AMIS 0.5um Tech (a) Basic Schematic (b) actual implementation 11/19/2018

Design Lab. – Self Bias Circuit with Temp. Compensation Simulation Results VDD Vr0b Vr0 (a) Vr0 (b) 11/19/2018

Design Lab. – Self Bias Circuit with Temp. Compensation Simulation Results – Temp. Compensation 90C 25C 90C 25C (a) (a) -10C -10C (b) (b) Vr0 Current 11/19/2018

Design Lab. – Self Bias Circuit with Temp. Compensation Zero Temperature Coefficient Point 90C 25C -10C 0.82V 11/19/2018

References Joongho Choi, “CMOS analog IC Design,” IDEC Lecture Note, Mar. 1999. B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2001. Hongjun Park, “CMOS Analog Integrated Circuits Design,” Sigma Press, 1999. 11/19/2018