Bipolar Processes Description EE 330 Bipolar Processes Description

Bipolar Process Description p-substrate epi 2

Components Shown Vertical npn BJT Lateral pnp BJT JFET Diffusion Resistor Diode (and varactor) Note: Features intentionally not to scale to make it easier to convey more information on small figures 3

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Area emitter factor is used to model other devices In contrast to the MOSFET where process parameters are independent of geometry, the bipolar transistor model is for a specific transistor ! Area emitter factor is used to model other devices Often multiple specific device models are given and these devices are used directly 13

D C A A’ B’ B C’ Top View D’ 14

Layer Mappings n+ buried collector isolation diffusion (p+) p-base diffusion n+ emitter contact metal passivation opening Notes: passivation opening for contacts not shown isolation diffusion intentionally not shown to scale 15

A A’ B’ B Dimmed features with A-A’ and B-B’ cross sections 16

A A’ B’ B 17

E C B vertical npn E B C lateral pnp C E C B E B 18

Diode (capacitor) G S D L W Resistor G D S n-channel JFET 19

Detailed Description of First Photolithographic Steps Only Top View Cross-Section View 20

A A’ B’ B n+ buried collector 21

Mask Numbering and Mappings n+ buried collector isolation diffusion (p+) p-base diffusion n+ emitter contact metal passivation opening Notes: passivation opening for contacts not shown isolation diffusion intentionally not shown to scale 22

Mask 1: n+ buried collector 23

n+ buried collector mask Exposure Develop Photoresist n+ buried collector mask Exposure Develop A-A’ Section B-B’ Section 24

Implant A-A’ Section B-B’ Section 25

Strip Photoresist A-A’ Section B-B’ Section 26

p-substrate A A’ n+ buried collector n+ buried collector B’ B 27

Grow Epitaxial Layer A-A’ Section B-B’ Section Note upward and downward diffusion of n+ buried collector B-B’ Section 28

Grow Epitaxial Layer p-substrate A’ A n+ buried collector 29

A A’ B’ B Isolation Diffusion 30

Mask Numbering and Mappings n+ buried collector isolation diffusion (p+) p-base diffusion n+ emitter contact metal passivation opening Notes: passivation opening for contacts not shown isolation diffusion intentionally not shown to scale 31

Mask 2: Isolation Deposition/Diffusion B’ B 32

Isolation Deposition/Diffusion A-A’ Section B-B’ Section 33

Isolation Diffusion p-substrate A’ A A A’ n+ buried collector 34

A A’ B’ B p-base diffusion 35

Mask Numbering and Mappings n+ buried collector isolation diffusion (p+) p-base diffusion n+ emitter contact metal passivation opening Notes: passivation opening for contacts not shown isolation diffusion intentionally not shown to scale 36

Mask 3: p-base diffusion 37

p-base Diffusion A-A’ Section B-B’ Section 38

p-base Diffusion p-substrate A’ A A A’ n+ buried collector 39

A A’ B’ B n+ emitter diffusion 40

Mask Numbering and Mappings n+ buried collector isolation diffusion (p+) p-base diffusion n+ emitter contact metal passivation opening Notes: passivation opening for contacts not shown isolation diffusion intentionally not shown to scale 41

Mask 4: n+ emitter diffusion B’ B 42

n+ emitter Diffusion A-A’ Section B-B’ Section 43

n+ emitter Diffusion p-substrate A’ A’ A A n+ buried collector 44

Oxidation A-A’ Section B-B’ Section 45

Oxidation p-substrate A’ A A n+ buried collector n+ buried collector B 46

A A’ B’ B contacts 47

Mask Numbering and Mappings n+ buried collector isolation diffusion (p+) p-base diffusion n+ emitter contact metal passivation opening Notes: passivation opening for contacts not shown isolation diffusion intentionally not shown to scale 48

Mask 5: contacts A A’ B’ B 49

Contact Openings A-A’ Section B-B’ Section 50

Contact Openings p-substrate A’ A A A’ n+ buried collector 51

A A’ B’ B metal 52

Mask Numbering and Mappings n+ buried collector isolation diffusion (p+) p-base diffusion n+ emitter contact metal passivation opening Notes: passivation opening for contacts not shown isolation diffusion intentionally not shown to scale 53

Mask 6: metal A A’ B’ B 54

Metalization A-A’ Section B-B’ Section 55

Pattern Metal A-A’ Section B-B’ Section 56

Metalization p-substrate A’ A A A’ A A’ n+ buried collector 57

Pattern Metal p-substrate A A’ A A’ B’ B n+ buried collector 58

E B C lateral pnp E C B vertical npn A-A’ Section C B E B C E B-B’ Section 59

G D S p-channel JFET A-A’ Section B-B’ Section 60

E C B vertical npn E B C lateral pnp C E C B E B 61

Diode (capacitor) G S D L W Resistor G D S n-channel JFET 62

Mask Numbering and Mappings n+ buried collector isolation diffusion (p+) p-base diffusion n+ emitter contact metal passivation opening Notes: passivation opening for contacts not shown isolation diffusion intentionally not shown to scale 63

Pad and Pad Opening p-substrate Epitaxial Layer Oxidation Metalization Protective Layer Pad Opening Mask Pad Opening 64

End of Lecture 19

The vertical npn transistor Emitter area only geometric parameter that appears in basic device model Transistor much larger than emitter Multiple-emitter devices often used (TTL Logic) and don’t significantly increase area

Enhancement and Depletion Devices Enhancement Mode n-channel devices VT > 0 Enhancement Mode p-channel devices VT < 0 Depletion Mode n-channel devices Depletion Mode p-channel devices

The JFET In triode region under reverse bias (channel thins)

The JFET In saturation (pinch-off) region under reverse bias and large VDS (channel pinches off)

The Schottky Diode Metal-Semiconductor Junction One contact is ohmic, other is rectifying Not available in all processes Relatively inexpensive adder in some processes Lower cut-in voltage than pn junction diode High speed

The MESFET Metal-Semiconductor Junction for Gate Drain and Source contacts ohmic, other is rectifying Usually not available in standard CMOS processes Must not forward bias very much Lower cut-in voltage than pn junction diode High speed

MOS and Bipolar Area Comparisions How does the area required to realize a MOSFET compare to that required to realize a BJT?

Consider Initially the Emitter in the BJT surrounded by a base region 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 Consider Initially the Emitter in the BJT surrounded by a base region 10 15 20 25 30 35 40 45 50 55

1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 10 15 20 4l 25 30 3l 35 40 45 50 55

1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 10 15 20 25 30 3l 2l 35 40 45 50 55

1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 10 15 20 19l 25 30 3l 2l 35 40 45 50 55

1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 10 15 20 23l 25 2l 30 3l 2l 35 40 45 50 55

1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 47l 10 15 20 23l 25 14l 14l 30 3l 2l 35 40 45 50 55

1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 51l 10 15 20 23l 25 14l 14l 14l 30 14l 3l 2l 35 40 45 50 55

1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 51l 10 15 20 23l 14l 25 14l 30 3l 2l 35 40 45 50 55

1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 51l 10 15 20 23l 14l 25 14l 30 3l 4l 2l 35 40 45 50 55

Note: 26l required Between p-base and isolation diffusion NOT TO SCALE 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 61l 10 15 20 14l 12l 25 19l 14l 2l 2l 2l 30 6l 3l 4l 2l 35 NOT TO SCALE Note: 26l required Between p-base and isolation diffusion 40 45 50 55

Note: Not to vertical Scale 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 71l 5 10 Note: Not to vertical Scale 14l 15 20 19l 25 12l 26l 44l 2l 30 6l 3l 2l 2l 35 Note: 26l required Between p-base and isolation diffusion 40 45 50 55

Note: Not to vertical Scale 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 71l 5 44l 10 Note: Not to vertical Scale 4l 15 20 25 12l 26l 2l 30 6l 3l 2l 2l 35 Note: 26l required Between p-base and isolation diffusion 40 45 50 55

Note: Not to vertical Scale 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 71l 5 44l 10 15 75l 20 48l 25 30 35 40 Note: Not to vertical Scale 45 50 55

Note: Not to vertical Scale 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 10 15 75l 20 48l 25 30 35 40 Bounding Area = 3600l2 45 Note: Not to vertical Scale 50 55

Comparison with Area for n-channel MOSFET in Bulk CMOS 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 10 Comparison with Area for n-channel MOSFET in Bulk CMOS 15 20 16l 25 13l 30 35 Bounding Area = 208l2 40 45 50 55

Minimum-Sized MOSFET Bounding Area = 168l2 Active Area = 6l2 14l 12l 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 10 Minimum-Sized MOSFET 15 20 14l 12l 25 30 35 Bounding Area = 168l2 Active Area = 6l2 40 45 50 55

Note: Not to vertical Scale 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 1 5 10 15 75l 20 48l 25 30 35 40 MOSFET BJT 45 50 Note: Not to vertical Scale 55

Area Comparison between BJT and MOSFET BJT Area = 3600 l2 n-channel MOSFET Area = 168 l2 Area Ratio = 21:1

End of Lecture 17