Topic 3c Integer Multiply and Divide Introduction to Computer Systems Engineering (CPEG 323) 2018/11/19 cpeg323-08F\Topic3c-323

Unsigned Integer Multiply Paper and pencil example: Multiplicand 1000 Multiplier * 1001 1000 0000 0000 1000 Product 01001000 2018/11/19 cpeg323-08F\Topic3c-323

Observation B0 A0 A1 A2 A3 B1 B2 B3 P0 P1 P2 P3 P4 P5 P6 P7 m bits * n bits = m+n bit product Stage i accumulates A * 2 i if Bi == 1 2018/11/19 cpeg323-08F\Topic3c-323

How does it work? B0 A0 A1 A2 A3 B1 B2 B3 P0 P1 P2 P3 P4 P5 P6 P7 at each stage shift A left ( x 2) use next bit of B to determine whether to add in shifted multiplicand accumulate 2n bit partial product at each stage 2018/11/19 cpeg323-08F\Topic3c-323

Simple Mathematics A*B If B has n bits, let the product be productn Then when B has n+1 bits 2i*A: shift A left for i times. It is clear that multiply is composed of iterative Shift and add 2018/11/19 cpeg323-08F\Topic3c-323

Multiply hardware (V1) Multiplicand 64 bits Multiplier 64-bit ALU Shift Left 64 bits Multiplier 64-bit ALU 32 bits Write Shift Right Product Control 64 bits Note: The multiplicand, Product and ALU are all 64-bits, while the Multiplier is 32-bits. 2018/11/19 cpeg323-08F\Topic3c-323

Multiply Algorithm (V1) 3. Shift the Multiplier register right 1 bit. Done Yes 2. Shift the Multiplicand register left 1 bit. No: < 32 repetitions 1. Test Multiplier0 Multiplier0 = 0 Multiplier0=1 1a. Add multiplicand to product & place the result in Product register 32nd repetition? Start Multiply Algorithm (V1) M’ier: 0011 M’and: 0000 0010 P: 0000 0000 1a. 1=>P=P+Mcand M’ier: 0011 Mcand: 0000 0010 P: 0000 0010 2. Shl Mcand M’ier: 0011 Mcand: 0000 0100 P: 0000 0010 3. Shr M’ier M’ier: 0001 Mcand: 0000 0100 P: 0000 0010 1a. 1=>P=P+Mcand M’ier: 0001 Mcand: 0000 0100 P: 0000 0110 2. Shl Mcand M’ier: 0001 Mcand: 0000 1000 P: 0000 0110 3. Shr M’ier M’ier: 0000 Mcand: 0000 1000 P: 0000 0110 1. 0=>nop M’ier: 0000 Mcand: 0000 1000 P: 0000 0110 2. Shl Mcand M’ier: 0000 Mcand: 0001 0000 P: 0000 0110 3. Shr M’ier M’ier: 0000 Mcand: 0001 0000 P: 0000 0110 1. 0=>nop M’ier: 0000 Mcand: 0001 0000 P: 0000 0110 2. Shl Mcand M’ier: 0000 Mcand: 0010 0000 P: 0000 0110 3. Shr M’ier M’ier: 0000 Mcand: 0010 0000 P: 0000 0110 2018/11/19 cpeg323-08F\Topic3c-323

Observations on Multiply Version 1 1/2 bits in multiplicand always 0 => 64-bit adder is wasted 0’s inserted in right of of multiplicand as shifted => least significant bits of product never changed once formed How many cycles it takes to multiply two 32-bit numbers ? 2018/11/19 cpeg323-08F\Topic3c-323

Instead of shifting multiplicand to left, shift product to right? 2018/11/19 cpeg323-08F\Topic3c-323

Multiply hardware (V2) Multiplicand 32 bits Multiplier 32-bit ALU Shift right Shift Right Product Control Write 64 bits NOTE: Note: Only Product are 64-bits, while the rest are all 32-bits. 2018/11/19 cpeg323-08F\Topic3c-323

Multiply Algorithm V2 Start Multiplier0=1 1. Test Multiplier0=0 1a. Add multiplicand to the left half of product & place the result in the left half of Product register 2. Shift the Product register right 1 bit. M’ier: 0011 Mcand: 0010 P: 0000 0000 1a. 1=>P=P+Mcand M’ier: 0011 Mcand: 0010 P: 0010 0000 2. Shr P M’ier: 0011 Mcand: 0010 P: 0001 0000 3. Shr M’ier M’ier: 0001 Mcand: 0010 P: 0001 0000 1a. 1=>P=P+Mcand M’ier: 0001 Mcand: 0010 P: 0011 0000 2. Shr P M’ier: 0001 Mcand: 0010 P: 0001 1000 3. Shr M’ier M’ier: 0000 Mcand: 0010 P: 0001 1000 1. 0=>nop M’ier: 0000 Mcand: 0010 P: 0001 1000 2. Shr P M’ier: 0000 Mcand: 0010 P: 0000 1100 3. Shr M’ier M’ier: 0000 Mcand: 0010 P: 0000 1100 1. 0=>nop M’ier: 0000 Mcand: 0010 P: 0000 1100 2. Shr P M’ier: 0000 Mcand: 0010 P: 0000 0110 3. Shr M’ier M’ier: 0000 Mcand: 0010 P: 0000 0110 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions 2018/11/19 cpeg323-08F\Topic3c-323 Done

What’s going on? Multiplicand stay’s still and product moves right B0 A0 A1 A2 A3 Multiplicand stay’s still and product moves right 2018/11/19 cpeg323-08F\Topic3c-323

Observations on Multiply Version 2 Product register wastes space that exactly matches size of multiplier => combine Multiplier register and Product register 2018/11/19 cpeg323-08F\Topic3c-323

Multiply hardware V3 Multiplicand 32 bits 32-bit ALU Product Control Shift right Product (Multiplier) Control Write 64 bits NOTE: now, the multiplier does need a separate register!! 2018/11/19 cpeg323-08F\Topic3c-323

Multiply Algorithm V3 Start Product0 = 1 1. Test Product0 Product0 = 0 1a. Add multiplicand to the left half of product & place the result in the left half of Product register Mcand: 0010 P: 0000 0011 1a. 1=>P=P+Mcand Mcand: 0010 P: 0010 0011 2. Shr P Mcand: 0010 P: 0001 0001 1a. 1=>P=P+Mcand Mcand: 0010 P: 0011 0001 2. Shr P Mcand: 0010 P: 0001 1000 1. 0=>nop Mcand: 0010 P: 0001 1000 2. Shr P Mcand: 0010 P: 0000 1100 1. 0=>nop Mcand: 0010 P: 0000 1100 2. Shr P Mcand: 0010 P: 0000 0110 2. Shift the Product register right 1 bit. 32nd repetition? Note: the multiplier is initially Placed in the right ½ of the Product Register No: < 32 repetitions Yes: 32 repetitions 2018/11/19 cpeg323-08F\Topic3c-323 Done

Sign Multiplication Easiest solution is to make both positive remember whether to complement product when done That is: calculate the sign of the product, convert the operands into positive numbers, leave out the sign bit, run for 31 steps, then fix the result. 2018/11/19 cpeg323-08F\Topic3c-323

Faster Algorithms for Multiplication Booth’s Algorithm multiply signed numbers using same hardware as before and save cycles can handle multiple bits at a time Using an array of adders Observation: whether to add or not add a particular shifted multiplicand – a decision can be made all in parallel .. 2018/11/19 cpeg323-08F\Topic3c-323

Divide: Paper & Pencil 1001 Quotient Divisor 1000 1001010 Dividend –1000 10 101 1010 –1000 10 Remainder Dividend = Quotient * Divisor + Remainder 2018/11/19 cpeg323-08F\Topic3c-323

Division Algorithm Input: Remainder register is initialized with the dividend; Divisor register is initialized in the left half; Quotient register is initialized with zero. Remainder register <= Subtract the Divisor register from the Remainder register ≥0 Test Remainder register <0 Shift the Quotient register to the left and setting the new rightmost to 1, Remainder register <= Remainder+Divisor Shift the Quotient register to the left and setting the new rightmost to 0 Shift the Divisor register right 1 bit no Repetition n+1 times? yes 2018/11/19 cpeg323-08F\Topic3c-323

How to do Division ? Shift Right Divisor 64 bits Quotient Shift Left Note: Dividend is NOT shifting, and Divisor is moving right! How to do Division ? Remainder Quotient Divisor 64-bit ALU Shift Right Shift Left Write Control 32 bits 64 bits How to do division here ? Note: Left ½ of Divisor R is initialized with the divisor, Remainder R is initialized with dividend, Quotient R is initialized with 0. Try to go over the example on P186. 2018/11/19 cpeg323-08F\Topic3c-323