Lecture 4 Single Cycle Machine Prof. Xiaoyao Liang 2015/3/18

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Presentation transcript:

Lecture 4 Single Cycle Machine Prof. Xiaoyao Liang 2015/3/18 MS108 Computer System I Lecture 4 Single Cycle Machine Prof. Xiaoyao Liang 2015/3/18

Notes

Basic Hardware

Register File

Memory

MIPS ISA

Life of an Instruction

Reg-Reg ALU

Reg-Imm ALU

Conflict in Merging Datapath

ALU Datapath

Memory Structure

Load/Store

MIPS Control

Conditional Branch (BNEZ)

Register Indirect Jump (JR)

Jump and Link (JALR)

Absolute Jump (J, JAL)

Single Cycle MIPS Datapath

Single Cycle Timing

Control Generation

Control Table