Semi-Symbolic Analysis of Analog and Signal Processing Systems

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Presentation transcript:

Semi-Symbolic Analysis of Analog and Signal Processing Systems Carna Radojicic, Florian Schupfer and Prof. Dr. Christoph Grimm

Overview Motivation State of the Art Proposed Solution Simulation results Conclusion 20.11.2018 Radojicic Carna

Motivation Accurate models -> Increase in model parameters Process variation -> Parameter deviations Efficient system analysis and verification methods 20.11.2018 Radojicic Carna

Motivation Verification of analog-mixed signal systems with parameter deviations Achieving full coverage with small number of simulation runs Numerical Simulation: Incomplete coverage High number of simulation runs Semi-symbolic simulation: Complete coverage for considered parameter space One simulation run 20.11.2018 Radojicic Carna

State of the Art Simulation based techniques Monte Carlo, Corner Case, Worst Case Design of Experiments[Rafaila] Importance sampling[Srinivasan] Formal verification techniques Model checking, Equivalence checking Hybrid verification[Henzinger] 20.11.2018 Radojicic Carna

Proposed solution Parameter deviations represented as ranges using Affine Arithmetic Semi-symbolic simulation Guaranteed result inclusion in one simulation run 20.11.2018 Radojicic Carna

Implementation Semi- symbolic simulation on system level – SystemC AMS Simulation on transistor level 20.11.2018 Radojicic Carna

Affine Arithmetic System deviations modeled in intervals Intervals labeled by symbols Symbols εi represent interval [-1, 1] xi is the numerical value which scales the interval Affine variable consists of nominal value and superimposed intervals 20.11.2018 Radojicic Carna

Graphical representations Range based system response Signal construction by sub-ranges 20.11.2018 Radojicic Carna

I/Q receiver with parameter deviations 20.11.2018 Radojicic Carna

Simulation results The bounds of output signal ranges represent the worst case behavior The principle for verification The system meets specification for the worst case -> The specification is satisfied for all values included into the range Formal verification result obtained inside the range 20.11.2018 Radojicic Carna

Simulation results The specification for the worst case not satisfied -> the system must be refined To refine the system the sources of uncertainties must be tracked back to their origin to be identified 20.11.2018 Radojicic Carna

Conclusion Efficient simulation performance Pessimistic worst case bounds  single run Traceable deviations influence Refinement information/recommendations 20.11.2018 Radojicic Carna

Thank You for Your Attention! Monika Rafaila, Christoph Grimm, Christian Decker, and Georg Pelz. Sequential design of experiments for effective model-based validation of electronic control units. e&i Elektrotechnik und Informationstechnik, 127:164–170, 2010. R. Srinivasan, Importance sampling - Applications in communications and detection, Springer-Verlag, Berlin, 2002. Darius Grabowski, Daniel Platte, Lars Hedrich, and Erich Barke. Time Constrained verification of Analog Circuits using Model-Checking Algorithms. Electronic Notes in Theoretical Computer Science (ENTCS), 153(3):37–52, 2006. 20.11.2018 Radojicic Carna