Digital Logic Design Digital Design, M. Morris Mano and Michael D

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https://sites.google.com/site/digitallogicdesigncourse1234/ Digital Logic Design Digital Design, M. Morris Mano and Michael D. Ciletti, 4rd edition, Prentice Hall Malik Najmus Siraj siraj@case.edu.pk 0321-5533938 https://sites.google.com/site/digitallogicdesigncourse1234/

Digital Logic Design@CASE by Najmus Siraj Today’s Agenda Recap Verilog code of flip flop Sequential design Verilog code of state machine Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Recap Digital Logic Design@CASE by Najmus Siraj

Verilog code of flip-flop module ff (input d, input clk, input rst, output reg q); always@(posedge clk) begin if (rst ==1) q <= 0; else q <= d; end endmodule Digital Logic Design@CASE by Najmus Siraj

Design of sequential circuit Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Finite State Machine Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Two flavors of FSM Digital Logic Design@CASE by Najmus Siraj

Design of sequential circuit Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Example 1 Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Example 1 Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Example 1 Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Example 1 Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Example 1 Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Example 1 Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Terminology Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Example 2 Description Design a clocked synchronous state machine with two inputs A and B, and a single output Z that is 1 if: A had the same value at each of the two previous clocks Or B has been 1 since the last time that the first condition was true Otherwise the output is 0 Digital Logic Design@CASE by Najmus Siraj

Verilog code of Sequence detector Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Module state_machine(input x, input clk, input rst, output reg y); parameter S0 = 2’d0; Parameter S1 = 2’d1; Parameter S2 = 2’d2; Parameter S3 = 2’d3; Reg [1:0]pState,nState; always@(posedge clk) begin if (rst) pState <= 2’d0; else pState <= nState; end always@(*) Case(pState) S0: if(x == 0) nState= S0; nState = S1; Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj S1: begin if(x == 0) nState= S0; else nState = S2; end S2: nState = S3; S3: endcase endmodule Digital Logic Design@CASE by Najmus Siraj

Digital Logic Design@CASE by Najmus Siraj Summary Design a finite state machine of a counter Digital Logic Design@CASE by Najmus Siraj