Dynamically Reconfigurable Architectures: An Overview Juanjo Noguera Dept. Computer Architecture (DAC-UPC) jnoguera@ac.upc.es

Outline Introduction Reconfigurable Computing Reconfigurable devices and systems Reconfigurable Systems Classification Reconfiguration Methods Reconfigurable Instruction Set Processors ASIP-based approach Coprocessor-based approach Conclusions

Introduction Reconfigurable Computing (RC) is an emerging paradigm for digital systems design Technology improvements have made possible new programmable logic devices (FPGAs, CPLDs) Objective of the talk: Give an overview of RC concepts and introduce the Reconfigurable Instruction Set Processors.

Introduction (II) RC objectives: Specialization, performance, flexibility Basic idea: “Programmable Hardware”  Specialization  Performance  Power consumption  Flexibility  Programming

Introduction (III) RC comparison versus other alternatives Performance Flexibility, Power GPP ASIC DSP RC Application Specific Systems General Purpose Systems Cost Performance Reconfigurable Computing

Outline Introduction Reconfigurable Computing Reconfigurable devices and systems Reconfigurable Systems Classification Reconfiguration Methods Reconfigurable Instruction Set Processors ASIP-based approach Coprocessor-based approach Conclusions

Reconfigurable Devices General device architecture Logic Bloc Interconnection Structure I/O Bloc Reconfigurable Computing

Reconfigurable Devices (II) Routing strategies A B C Continuous Routing Structured Routing Reconfigurable Computing

Reconfigurable Devices (III) SRAM based devices with infinite number of reconfigurations App 1 -> Bitstream 1 App 2 -> Bitstream 2 App n -> Bitstream n Configuration Bitstream 110011101 ... Reconfigurable Computing Reconfigurable Device

Reconfigurable Systems (I) Rapid System (ASIC) Prototyping Reconfigurable Computing CPU PLD PLD PLD PLD PLD

Reconfigurable Systems (II) Reconfigurable Systems Classification Host Computer (d) PLD CPU Reconfigurable Computing (c) RAM PLD SYSTEM BUS PLD RAM PLD I/O (b) RAM (a)

Reconfiguration Methods (I) Compile Time Reconfiguration (CTR) Device configuration is fixed during application run time execution Run Time Reconfiguration (RTR) Device configuration changes during application run time execution RTR strategies Global RTR Partial RTR Reconfigurable Computing

Reconfiguration Methods (II) Global Run Time Reconfiguration (Single context) Application Execution #1 Execution Reconfiguration #2 Reconfiguration #2 Reconfigurable Computing Reconfiguration #4 Execution #3 #4 Reconfiguration Contexts #1 Dynamically Reconfigurable Device

Reconfiguration Methods (III) Partial Run Time Reconfiguration (Multiple context) Aplicació #1 Reconfiguration #4 #1 #2 #2 Reconfigurable Computing #3 #4 #4 #1 Reconfiguration Contexts #3 Dynamically Reconfigurable Device

Reconfiguration Methods (IV) Run-Time Reconfiguration Challenges Temporal Partitioning Context Scheduling (static) Reconfiguration Latency Overhead Configuration Pre-fetching Configuration Caching Configuration Compression Reconfigurable Computing

Outline Introduction Reconfigurable Computing Reconfigurable devices and systems Reconfigurable Systems Classification Reconfiguration Methods Reconfigurable Instruction Set Processors ASIP-based approach Coprocessor-based approach Conclusions

Reconfigurable Instruction Set Processors Reconfigurable Processor Introduction By including reconfigurability we can increase flexibility with high specialization Reconfigurable Instruction Set Processors Processor PLD Reconfigurable Processor

Reconfigurable Instruction Set Processors Introduction (II) Coprocessor based approach ASIP based approach · · · Task 1 Task K Task K+1 Task N Software Hardware Reconfigurable Instruction Set Processors Task 1 Task 2 Task N Software Hardware · · ·

Coprocessor based approach (I) Typical example: CPU + PCI board Altera ARC-PCI Compaq Pamette System on Chip (SoC) Altera´s Excalibur device Chameleon Systems, Inc. Reconfigurable Instruction Set Processors

Coprocessor based approach (II) Altera ARC-PCI Reconfigurable Instruction Set Processors

Coprocessor based approach (III) Compaq Pamette Reconfigurable Instruction Set Processors

Coprocessor based approach (IV) Altera´s Excalibur device Embedded Processor: ARM, MIPS or NIOS Reconfigurable Instruction Set Processors

Coprocessor based approach (V) Chameleon Systems, Inc. Reconfigurable Instruction Set Processors

ASIP based approach (I) Reconfigurable unit within CPU Fetch Decode Issue Integer Unit FP Branch LD/ST Reconfigurable Reconfigurable Instruction Set Processors

ASIP based approach (II) Challenge: CAD tools C Code Compiler Assembly Code Instruction Description (Configuration bits) Reconfigurable Instruction Set Processors

ASIP based approach (III) C Parsing Optimizations Inst. Identification Inst. Selection Config. Scheduling Code Generation C Code Assembly Code Hardware Generation Configuration bits Estimator Compiler Structure Reconfigurable Instruction Set Processors

ASIP based approach (II) Example: Philips CinCISe Architecture Encoded Instruction Word Register File ALU RFU MUX 5 4 32 Reconfigurable Instruction Set Processors

ASIP based approach (III) Application example: DES & A5 encryptation algorithms 27 26 25 23 22 30 7 6 5 4 3 2 27 26 25 22 XOR Reconfigurable Instruction Set Processors srl $13, $2, 20 andi $25, $13, 1 srl $14, $2, 21 andi $24, $14, 6 or $15, $25, $24 srl $13, $2, 22 andi $14, $13, 56 or $25, $15, $14 sll $24, $25, 2 srl $24, $5, 18 srl $25, $5, 17 xor $8, $24, $25 srl $9, $5, 16 xor $10, $8, $9 srl $11, $5, 13 xor $12, $10, $11 andi $13, $12, 1

Conclusions Reconfigurable Computing is an emerging and interesting computing paradigm RC devices and architectures are becoming a reality There is a big challenge is High-level synthesis (CAD) tools

Conclusions (II) ?? What is the future ?? Flexibility, Power RC GPP RC DSP RC RC ASIC Performance