332:437 Lecture 15 System Controller Design Mnemonic Documented State Diagram Timing Diagram Flow Diagram Summary Material from An Engineering Approach to Digital Design, by William I. Fletcher, Englewood Cliffs, NJ: Prentice-Hall 11/20/2018 Bushnell: Digital Systems Design Lecture 15

Multi-Input System Controller Design General System Level Design Special Sequential Machine – interprets system level control input sequences and generate system level and pulse output sequences Controls a data path consisting of Registers, MUXes, etc. Nerve Center – Has many control inputs & outputs 11/20/2018 Bushnell: Digital Systems Design Lecture 15

Example System Controller 11/20/2018 Bushnell: Digital Systems Design Lecture 15

Controller Implementation In many cases, the system controller will be implemented by a mprocessor and a ROM Follow a structured design procedure It leads to much less work 11/20/2018 Bushnell: Digital Systems Design Lecture 15

Bushnell: Digital Systems Design Lecture 15 Design Procedure Know what you are going to do & how you are going to do it Design documentation should be a natural outcome of your work Document your work so that you and others can understand it 11/20/2018 Bushnell: Digital Systems Design Lecture 15

Bushnell: Digital Systems Design Lecture 15 Design Process Define the purpose and role of the digital system in English writing. Define the logic operations & limitations of the systems that the system controller is to control (Data Path Synthesis). Aided by designing a first-cut flow diagram and logic clock diagram Leads to Functional Partition 11/20/2018 Bushnell: Digital Systems Design Lecture 15

Design Process (continued) Create timing diagram – Define timing & frequency of system level input & output control signals. Note any specific timing constraints. Detail sequential behavior of system controllers. Determine registers, temporary storage, special circuit & other subfunction requirements. For system controller & overall system 11/20/2018 Bushnell: Digital Systems Design Lecture 15

Design Process (continued) Develop detailed timing diagrams for system level & subfunction control. Develop Mnemonic Documented State Diagram (MDS) for system controller. 11/20/2018 Bushnell: Digital Systems Design Lecture 15

Mnemonic Documented State Diagram for Controller 11/20/2018 Bushnell: Digital Systems Design Lecture 15

Bushnell: Digital Systems Design Lecture 15 Controller Timing Diagram 11/20/2018 Bushnell: Digital Systems Design Lecture 15

Controller Flow Diagram 11/20/2018 Bushnell: Digital Systems Design Lecture 15

Bushnell: Digital Systems Design Lecture 15 MDS Diagram State labeled with * to indicate that branching (from state) is controlled by an asynchronous input Level/ Pulse notation Means assert a signal (no voltage level implied) Means deassert (no voltage level implied) 11/20/2018 Bushnell: Digital Systems Design Lecture 15

MDS Diagram (Continued) Means output a pulse, synchronous either with a clock or with the presence in a state or both Design System Controller Flow Diagram – Like a Software Flow Chart but for hardware 11/20/2018 Bushnell: Digital Systems Design Lecture 15

Timing Frequency Considerations At what point in time can a controlling input be expected? Is it synchronous or asynchronous? How long will input be asserted? How much time elapses after the input until a control output is expected? When must the control signal be issued in the time frame? How long with the output signal remain asserted? 11/20/2018 Bushnell: Digital Systems Design Lecture 15

Bushnell: Digital Systems Design Lecture 15 Hardest Part Create Functional Partition Detailed Flow Diagram Detailed Timing diagram 11/20/2018 Bushnell: Digital Systems Design Lecture 15

Bushnell: Digital Systems Design Lecture 15 Five Concepts Action block in Flow Diagram corresponds to a state in MDSD State Diagram begins & ends with an action clock Branching condition for state in MDS Diagram found by tracing decision paths in Flow Diagram 11/20/2018 Bushnell: Digital Systems Design Lecture 15

Five Concepts (continued) Avoid making branching decision in one state based on >1 asynchronous inputs Generalized outputs symbolized by action notation in action blocks Unconditional & conditional outputs specified with duration time dependent on an input variable 11/20/2018 Bushnell: Digital Systems Design Lecture 15

Bushnell: Digital Systems Design Lecture 15 Summary System Controller Design Mnemonic Documented State Diagram Timing Diagram Flow Diagram 11/20/2018 Bushnell: Digital Systems Design Lecture 15