Virtual Memory 15213-S04, Recitation, Section A Exam 2 Issues Virtual Memory Cache structure

Exam 2 Times Topics This Thursday, 9pm Review Session: This Tuesday Virtual Memory Cache Structure System I/O Exceptional Control Flow Signals Linking Cache Performance

Cache Structure & Performance Set size, line size (block size) Physical address is split to 3 parts for cache: … One cache miss will trigger a … size of memory being fetched Eg: line size 32 bytes, sequentially reading a large char array will have cache miss rate: …. Direct-mapped, N-way associative In directed-mapped, reading two different addresses with the same set index will … In 2-way associative, reading two different addresses with the same set index will …

System I/O How many structures are involved in the file handling? What are the two main ways of sharing file? Any difference?

Exception Control & Signaling fork(), waitpid(), execve(), kill(), signal(), … (textbook!)

Linking Linker Symbol Rule? Shared Library, Library interposition? Strong and weak symbols? Shared Library, Library interposition?

Overview of P6 Address Translation CPU 32 L2 and DRAM result 1 2 3 4 20 12 virtual address (VA) VPN VPO L1 miss L1 hit 16 4 TLBT TLBI L1 (128 sets, 4 lines/set) TLB hit TLB miss ... ... 10 10 TLB (16 sets, 4 entries/set) VPN1 VPN2 20 12 20 7 5 PPN PPO CT CI CO physical address (PA) PDE PTE Page tables PDBR

Cache Structure 1-byte word 13-bit physical address 4-way associative cache, 4-byte block, 32 line