Topic 6: Pipelining and Pipelined Architecture 2018/11/20 \course\cpeg323-05F\Topic6-323.ppt
Reading List Slides: Topic6x Henn & Patt: Chapter 6 Other papers as assigned in class or homeworks 2018/11/20 \course\cpeg323-05F\Topic6-323.ppt
Pipelining What is pipelining - basic concepts Pipelined datapath: A case study of MIPS Pipeline control Pipeline hazard resolution 2018/11/20 \course\cpeg323-05F\Topic6-323.ppt
Pipelining – the basic concepts 2018/11/20 \course\cpeg323-05F\Topic6-323.ppt
Basic Concept Pipeline: multiple instructions are simultaneously in execution Pipeline is divided into “segments” or “stages” Machine cycle: Time required to move through one stage Machine cycle is determined by the slowest stage in the pipe Often Machine Clock cycle cycle = 2018/11/20 \course\cpeg323-05F\Topic6-323.ppt
In a perfectly balanced pipelined machine instruction time = In a normal machine (1) is not true, i.e. - stage time does not equal there is overhead but it can be very close to 10% within (1) non-pipe time # of pipe stages (1) 2018/11/20 \course\cpeg323-05F\Topic6-323.ppt
Pipelining as an Architecture Technique Generally may be invisible to user Scalar pipelined machine vs. vector machine 2018/11/20 \course\cpeg323-05F\Topic6-323.ppt
# of instructions cycle completed Pipeline throughout So pipeline increases throughout, but the time for execution of each instruction remains unchanged. Clock rate of a pipelined machine is limited by: latch time clock skew the delay time required for clock signals to propagate on a chip. # of instructions completed cycle 2018/11/20 \course\cpeg323-05F\Topic6-323.ppt
Performance Limitations of a Pipeline Rate cannot exceed the slowest stage Complexities in reality different processing time for different stages interaction/dependencies between stages - may be data dependent (dynamic) 2018/11/20 \course\cpeg323-05F\Topic6-323.ppt
The most important factors on “pipe beat” (cycle time) STAGE 1 LACHES Combinational Logic STAGE 2 LACHES STAGE 3 LACHES STAGE n LACHES (b) The most important factors on “pipe beat” (cycle time) latch delay and clock skew 2018/11/20 \course\cpeg323-05F\Topic6-323.ppt
Overlap vs. Pipeline Pipeline: tightly coupled subfunctions fixed basic stage time independent basic function evaluation Overlap Loosely coupled subfunctions variable basic stage time dependency between function evaluation 2018/11/20 \course\cpeg323-05F\Topic6-323.ppt
CPU/I/O Overlapping Common memory Computational processor (stage 1) Input/output processor (stage 2) 1 Task 1 Task 2 Task 1 Task 3 . . . 2 Task 2 Task 1 Task 3 Task 1 Time =Idle time CPU/I/O Overlapping 2018/11/20 \course\cpeg323-05F\Topic6-323.ppt
Static vs. Dynamic Pipeline - only repeated evaluations of the same function with different data are performed - no dynamic data dependencies between initiations - fixed pattern of initiations Dynamic: opposite to static (asynchronous) (overlapping) Example of static pipeline: Float-point addition pipeline 2018/11/20 \course\cpeg323-05F\Topic6-323.ppt
Uni-Function vs. Multi-Function Pipeline Uni-function pipe example: addition pipe Multi-Function pipe example arithmatic pipe Vector Pipe Programmable pipe control (Vector instruction determines the function and inputs) 2018/11/20 \course\cpeg323-05F\Topic6-323.ppt
MIPS Pipeline Pipeline stages: IF ID (decode + Reg fetch) EX MEM Write back On each clock cycle another instruction is fetched and begins its five-step execution. If an instruction is started every clock cycle, the performance will be five times that of a machine that is not pipelined. 2018/11/20 \course\cpeg323-05F\Topic6-323.ppt
MIPS Pipeline - Another Representation 2018/11/20 \course\cpeg323-05F\Topic6-323.ppt