Capacitor Charging: Voltage Across Sample & Hold Capacitor Voltage across the sampling capacitor changes with a single-pole response during the CDAC-SAR ADC acquisition period. During the acquisition time, the voltage on the sampling capacitor needs to change from the initial voltage VSH0 to the final value of VIN. It is important that at the end of the acquisition time, the voltage difference on the sampling capacitor and input voltage is less than 1/2LSB. If you consider the ADC input exclusively, the input bandwidth of the ADC depends on the internal sampling capacitor, CSH, and the switch resistance, RS1. From the time constant, τ = RS1×CSH, we can derive the settling time of this one pole system. The minimum acquisition time for the CDAC-SAR converter is the time required for the sampling mechanism to capture the input voltage. This acquisition time begins after the sample command is given and the hold capacitor, CSH, charges. We can determine the settling time for the ADC equivalent input network with the above equations. VCSH(t) is voltage in time across the sampling capacitor, CSH VCSH(t0) is voltage across the CSH, at beginning of acquisition time VIN is the input voltage to the ADC τ is the acquisition time constant and equal to RS1 × CSH t is a time variable in seconds Assuming Vcsh(to)=0 and VIN is close to full scale; the user may have to wait several Time constants (T) for the sampling capacitor to charge within ½ LSB… (N+1)Ln(2) = 11.78 time constants for a 16 bit, 10.39 for a 14 bit, 9.01 for a 12 bit.