Dominique Breton, Jihane Maalmi

Slides:



Advertisements
Similar presentations
U N C L A S S I F I E D FVTX Detector Readout Concept S. Butsyk For LANL P-25 group.
Advertisements

PicoTDC Features of the picoTDC (operating at 1280 MHz with 64 delay cells) Focus of the unit on very small time bins, 12ps basic, 3ps interpolation Interpolation.
NA62 Trigger Algorithm Trigger and DAQ meeting, 8th September 2011 Cristiano Santoni Mauro Piccini (INFN – Sezione di Perugia) NA62 collaboration meeting,
LHCb front-end electronics and its interface to the DAQ.
CERN, 18 december 2003Coincidence Matrix ASIC PRR Coincidence ASIC modifications E.Petrolo, R.Vari, S.Veneziano INFN-Rome.
18/05/2000Richard Jacobsson1 - Readout Supervisor - Outline Readout Supervisor role and design philosophy Trigger distribution Throttling and buffer control.
APV25, Clock and Trigger M.Friedl HEPHY Vienna. 2Markus Friedl (HEPHY Vienna)18 Mar 2009 APV25 Please refer to my December 2008 meeting slides for details.
Juin 1st 2010 Christophe Beigbeder PID meeting1 PID meeting Electronics Integration.
1 Timing of the calorimeter monitoring signals 1.Introduction 2.LED trigger signal timing * propagation delay of the broadcast calibration command * calibration.
SuperB DAQ U. Marconi Padova 23/01/09. Bunch crossing: 450 MHz L1 Output rate: 150 kHz L1 Triggering Detectors: EC, DC The Level 1 trigger has the task.
SuperB FCTS/DAQ Protocol Steffen Luitz and Gregory Dubois-Felsmann SuperB Computing Workshop, Frascati 12/17/08.
C.Beigbeder, D.Breton, M.El Berni, J.Maalmi, V.Tocut – LAL/In2p3/CNRS L.Leterrier, S. Drouet - LPC/In2p3/CNRS P. Vallerand - GANIL/CNRS/CEA SuperB -Collaboration.
November 16th 2011 Christophe Beigbeder 1 ETD meeting PID Integration.
SuperB-DCH S ervizio E lettronico L aboratori F rascati 1LNF-SuperB Workshop – September 2010G. Felici DCH FEE STATUS Some ideas for Level 1 Triggered.
ETD/Online Summary D. Breton, U. Marconi, S. Luitz Frascati Workshop 04/2011.
Some thoughs about trigger/DAQ … Dominique Breton (C.Beigbeder, G.Dubois-Felsmann, S.Luitz) SuperB meeting – La Biodola – June 2008.
Serial link Loss-of-Lock impact on trigger distribution dead time
Work on Muon System TDR - in progress Word -> Latex ?
Error Correcting Codes for Serial links : an update
DCH FEE STATUS Level 1 Triggered Data Flow FEE Implementation &
ETD meeting Architecture and costing On behalf of PID group
Defining serial links for SuperB
ETD meeting First estimation of the number of links
APSEL6D Architecture, simulations and results
Electronics Trigger and DAQ CERN meeting summary.
ETD summary D. Breton, S.Luitz, U.Marconi
Electronics for SuperB DAQ
ETD/Online Report D. Breton, U. Marconi, S. Luitz
CERN meeting report, and more … D. Breton
Trigger, DAQ and Online Closeout
Status of ETD/Online D. Breton, U.Marconi, S.Luitz
Modelisation of SuperB Front-End Electronics
ETD meeting Electronic design for the barrel : Front end chip and TDC
SuperB FCTS/DAQ Protocol Proposal Tradeoffs
From SNATS to SCATS C. Beigbeder1, D. Breton1,F.Dulucq1, L. Leterrier2, J. Maalmi1, V. Tocut1, Ph. Vallerand3 1 : LAL Orsay, France (IN2P3 – CNRS) 2 :
PID meeting SCATS Status on front end design
ETD/Online Report D. Breton, U. Marconi, S. Luitz
ETD/Online Summary D. Breton, U. Marconi, S. Luitz
Christophe Beigbeder PID meeting
DCH FEE 28 chs DCH prototype FEE &
Electronics, Trigger and DAQ for SuperB
SLP1 design Christos Gentsos 9/4/2014.
Discussion after electronics parallel session
Trigger, DAQ, & Online: Perspectives on Electronics
Modelisation of control of SuperB Common Front-End Electronics
Vertex 2005 November 7-11, 2005 Chuzenji Lake, Nikko, Japan
EMC Electronics and Trigger Review and Trigger Plan
FPGA-based Time to Digital Converter and Data Acquisition system for High Energy Tagger of KLOE-2 experiment L. Iafolla1,4, A. Balla1, M. Beretta1, P.
Example of DAQ Trigger issues for the SoLID experiment
Impact of Serializer/Deserializer Architecture on ETD High-Speed Links
Dynamic Packet-filtering in High-speed Networks Using NetFPGAs
ETD/Online Summary D. Breton, U. Marconi, S. Luitz
PID electronics for FDIRC (Focusing Detector of Internally Reflected Cherenkov light) and FTOF (Forward Time of Flight) Christophe Beigbeder and Dominique.
Tests Front-end card Status
Throttling: Infrastructure, Dead Time, Monitoring
SuperB FCTS/DAQ Protocol Proposal
PID meeting Mechanical implementation Electronics architecture
ETD parallel session March 18th 2010
SVT detector electronics
APV25, Clock and Trigger M.Friedl HEPHY Vienna.
Electronics, trigger and DAQ for SuperB.
for the trigger subsystem working group:
Electronics for the PID
Electronics, Trigger and DAQ for SuperB: summary of the workshop.
Moving towards Elba and the TDR …
The LHCb Front-end Electronics System Status and Future Development
U. Marconi, D. Breton, S. Luitz
Fixed Latency Serial Links with FPGA-embedded SerDes for SuperB
Links and more … D. Breton
LNF PID session 1 December 1st 2009
Presentation transcript:

Dominique Breton, Jihane Maalmi Sizing of the front-end derandomizer: simulation of the hardware Verilog model Dominique Breton, Jihane Maalmi

Jihane Maalmi –Dominique Breton- Elba - May 2011 Aim of this study This study was triggered by discussions between Steffen, Umberto and Dominique, in the wake of the last February CERN ETD meeting Its goal is to get a first flavour of the necessary derandomizer depth in order to have a limited dead-time. At the last workshop in Frascati, Steffen presented the first simulations, performed with SimPy Those were running a simplified model of the derandomizer elements They produced clean and useful preliminary results In parallel, we started working on Verilog simulations based on the front-end implementation presented in the former workshops In this present talk, first simulations of this actual hardware implementation will be shown Environment and all effective parameters will be described Jihane Maalmi –Dominique Breton- Elba - May 2011

General Architecture of SuperB Electronics Jihane Maalmi –Dominique Breton- Elba - May 2011

Constraints concerning the Trigger Trigger window : Long latency (~ 6 µs) + jitter, due to machine and detector constraints, >> potentiallly large trigger window (1µs max) for data readout - The trigger window will be adjusted depending on the sub-detector in order to optimize the dataflow: It will be fixed but programmable in the FEE Consecutive Triggers : - No minimum distance fixed at the architecture level. - Min ~ 70 ns (highly probable) due to the time precision of trigger. - No limitation fixed for their number in a burst. => Those constraints should only depend on the trigger system itself Problems : - Two consecutive physics events may reside within the trigger time window (overlapping). FEE should be able to deal with close triggers (Overlapping), and send data in consequence (reducing the size of posterior events) Jihane Maalmi –Dominique Breton- Elba - May 2011

Simulation of synchronous model The FCTS sends a L1 trigger command optionally associated with a value corresponding to a time window. The FEE sends to the DAQ (ROM) the data contained inside a readout window, embedded in a frame including status, trigger tag and time, and length of data field. Trigger is defined by three parameters: - The latency: L (fixed in the FEE) - The readout window: W (fixed in the FEE and sub-detector dependent) - The time distance between triggers: D (measured in the FEE) Constraints : - Minimum dead time in data processing - Triggers with potentially overlapping windows

Jihane Maalmi –Dominique Breton- Elba - May 2011 Parameter Definition t0 L1 Trigger #0 Data to keep Data to dump L W Time M Baseline: latency pipeline always provides the oldest relevant data L: fixed latency W: window containing the relevant data for trigger #0 M: data sent to ROM Jihane Maalmi –Dominique Breton- Elba - May 2011

Jihane Maalmi –Dominique Breton- Elba - May 2011 Synchronous Model with a fixed readout window L : Latency W : Window D : Distance between triggers M : data sent to ROM Case 1 : D ≥ W Trigger #0 Trigger #1 D Non overlapping latencies with 2 different windows (green): no problem M1 = W L D ≥ L W W M0 M1 Trigger #0 Trigger #1 Overlapping latency trigger with overlapping windows: trickier … The window W1 is then shortened! M1 = W – (W – D)= D Case 2 : D < W D W M0 W M1 Jihane Maalmi –Dominique Breton- Elba - May 2011

Jihane Maalmi –Dominique Breton- Elba - May 2011 Synchronous model: dealing with Overlapping Case 1 : Dn ≥ W : Mn = W Case 2 : Dn < W : Mn = Dn Mn : amount of data to send to ROM for trigger #n Trigger input Counter Dn Dn ≥ W? Clock 56 MHz W Fifo “M” !empty M U X Mn FSM W end enable W Mn Counter Registers L All 56 MHz synchronous pipelined operations Start_flag, Mn to serializer Wr_en Data input Latency Pipeline Derandomizer L Jihane Maalmi –Dominique Breton- Elba - May 2011

Parameter definition for derandomizer simulation (1) The derandomizer is the buffer located just behind the latency buffer and in front of the readout serializer. Its role is to absorb the difference in dataflow rate between the gated output of the latency buffer (exponential distribution of the distance between events) and the input of the serializer (fixed dataflow). This part of the system is defined by three parameters: - The average trigger rate: R[Events/s] (150 kEvents/s by default) - The readout window: W[Nb of 56MHz clock periods] (fixed in the FEE and sub-detector dependent) - The number of channels multiplexed at the output of the derandomizer to feed the link: N Default assumption : - Serializer is sending (or makes an equivalent job) 32-bit words at a rate of 56 MHz => 1.8 Gbits/s

Jihane Maalmi –Dominique Breton- Elba - May 2011 Model of the derandomizer environment Derandomizer Output State Machine All 56 MHz synchronous pipelined operations Almost_full Derandomizer Input State Machine L1 Trigger Clock 56 MHz Rd Derandomizer Wr Ch0 Latency Pipeline 32Bits SERDES L Serial link W M U X L Registers Derandomizer Wr_en Clk 56MHz ChN-1 Latency Pipeline Rd Jihane Maalmi –Dominique Breton- Elba - May 2011

Parameter definition for derandomizer simulation (2) The other important parameter is the mean link occupancy. It is defined by the ratio between the average link payload and its nominal capacity In our case: The nominal capacity is 1.8 Gbits/s The payload is: 32[bits] . R[kHz] . W . N For instance, with a payload of 1.44 Gbits/s, the ratio is 80% It has to be noticed that: R is a constant at the experiment level (150 kHz) W is sub-detector dependent N has to be defined by sub-detector In order to “feel” the influence of this ratio, think about a derandomizer where the ration is equal to 100%, fill it up with a burst, and wonder how long it may take to empty it …

Introducing the dead time … The goal of these simulations is to get a first flavour of the necessary derandomizer depth in order to have a limited dead-time. Due to the fact that the minimum distance between triggers is not “zero”, the minimum achievable dead-time is not zero either. For instance, there is a constant term of: ~0.45% at 30 ns ~0.75% at 50 ns ~1.05% at 70 ns ~1.5% at 100 ns In the following simulations, we took 50 ns as arbitrary hypothesis and looked for the derandomizer depth necessary to end up with a dead-time of 1%. The main variable parameters are: The window length (W): That way, the effect of pile-up can be studied Different link ratios are studied Other parameter remain constant : R = 150 kEvents/s

Simulation Result Trigger Mean Rate : 150 kHz , Min Inter Trigger Distance = 50 ns, Required dead time : between 0,9 % and 1,1 % W varying between 10 and 55 (180 ns to 990 ns); Mean Link Occupancy (or Ratio): between 0.5 and 0.95 Result : Derandomizer Depth [Nb of full events] Derandomize Depth Ratio or Mean link Occupancy

Simulation Result (2) Trigger Mean Rate : 150 kHz , Min Inter Trigger Distance : varying 30,50,70 ns Required dead time : between 0,9 % and 1,1 % Mean Link Occupancy (or Ratio): 0.8 W varying between 10 and 55 (180 ns to 990 ns); Result : Derandomizer Depth [Nb of full events] Derandomize depth Window

Simulation Result s(3) Dead Time ( W) W varying between 10 and 40; Plot1 : Trigger Mean Rate : 150 kHz Min Inter Trigger Distance : 30 ns For a link with mean link occupancy = 0.8 With same obtained derandomizer depth, and without changing the multiplexing factor (N) : Plot 2 : Upgrade : Trigger Mean Rate 300 kHz, Min Distance 30 ns Mean link occupancy > 100%  dead time increases by a factor 35!! Dead time W

Remarks The problem is very different if one looks at detectors with opposite behaviors: short time window, high multiplexing factor and reduced pile-up (and possibly variable event size) => ~SVT, Forward and Barrel PID, Backward EMC, IFR long fixed time window, low multiplexing factor and high pile-up probability => DCH, Forward and Barrel EMC In the case of variable event size, what should we base the derandomizer depth on: - The average size ? (less depth but more potential pile-up) - The maximum size ? (minimum dead-time but maximum depth) Importance of a fast throttle Problem : how to implement a model of the derandomizer if the event size is random (to build the throttle )? The worst case will depend on the sub-detector implementation We may need a fast direct throttle between FEE and FCTS Return path of clock and control links could be used therefore

Conclusion We started simulating the FEE hardware Verilog model in order to estimate the necessary derandomizer depth to keep the dead-time at a reasonable level Therefore, we defined all the parameters linked to the derandomizer environment First results show that the link occupancy ratio has a great influence on the derandomizer depth Pile-up helps ! … We have to optimize the code to extract the required information more easily We need to compare our results with Steffen’s The final goal of the study is to give to subdetectors a table with the necessary derandomizer depth and link occupancy ratio with respect to the width of their own trigger time window