Day 37: December 2, 2013 Transmission Lines Modeling and Termination ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 37: December 2, 2013 Transmission Lines Modeling and Termination Penn ESE370 Fall2013 -- DeHon

Transmission Line Agenda See in action in lab Where arise? General wire formulation Lossless Transmission Line Impedance End of Transmission Line? Termination Discuss Lossy Implications Penn ESE370 Fall2013 -- DeHon

From Day 36 Signal propagate as wave down transmission line V(x,t) = A+Be(x-wt) Delay linear in wire length Speed Penn ESE370 Fall2013 -- DeHon

Wire “Resistance” What is the resistance at Vi ? Q to charge Vi? Ii given velocity w? R = Vi/Ii? Ii+1 Ii Vi-1 Vi Vi+1 Ici Penn ESE370 Fall2013 -- DeHon

Wire “Resistance” Q=CV I = dQ/dt Moving at rate w I=wCV R=V/I=1/(wC) Ii+1 Ii Vi-1 Vi Vi+1 Ici Penn ESE370 Fall2013 -- DeHon

Impedance Z0 =R= 1/wC = 1/(C/sqrt(LC)) Ii+1 Ii Vi-1 Vi Vi+1 Ici Penn ESE370 Fall2013 -- DeHon

Impedance Assuming infinitely long wire, how look different at Vi, Vi+1, Vi+2 ? Ii+1 Ii Vi-1 Vi Vi+1 Ici Penn ESE370 Fall2013 -- DeHon

Impedance Transmission line has a characteristic impedance Looks to driving circuit like a resistance Penn ESE370 Fall2013 -- DeHon

Infinite Lossless Transmission Line Transmission line looks like resistive load Input waveform travels down line at velocity Without distortion Z0 Penn ESE370 Fall2013 -- DeHon

End of Line What happens at the end of the transmission line? Short Circuit Hint: what must happen in steady state? Terminate with R=Z0 Open Circuit Penn ESE370 Fall2013 -- DeHon

Short Penn ESE370 Fall2013 -- DeHon

Terminate R=Z0 Penn ESE370 Fall2013 -- DeHon

Open Penn ESE370 Fall2013 -- DeHon

Longer LC (open) 40 Stages L=100nH C=1pF Stage delay? Drive with 2ns Pulse No termination (open circuit) Penn ESE370 Fall2013 -- DeHon

Pulse Travel RC V1,V3,V4,V5,V6 about 10 stages apart Penn ESE370 Fall2013 -- DeHon

Analyze End of Line Penn ESE370 Fall2013 -- DeHon

Analyze End of Line Incident wave Vi=Ii×Z0 @ T-e Vi is voltage on line Vt is what goes forward Voltage seen by end of line at T Vr is the delta voltage that starts moving back towards source at T+e Penn ESE370 Fall2013 -- DeHon

Analyze End of Line Incident wave Vi=Ii×Z0 KCL @ end KVL @ end V=IR relationships? Which resistances go with each V? Relate all three V’s using R, Z0 Penn ESE370 Fall2013 -- DeHon

Analyze End of Line Incident wave Vi=Ii×Z0 KCL: Ii=Ir+It KVL: Vi+Vr=Vt Vr=Ir×Z0 Ir=Vr/Z0 Vt=It×R It=Vt/R Ii=Vi/Z0 Penn ESE370 Fall2013 -- DeHon

Analyze End of Line Vi+Vr=Vt Eliminate Vt Penn ESE370 Fall2013 -- DeHon

Analyze End of Line Vi+Vr=Vt Penn ESE370 Fall2013 -- DeHon

Analyze End of Line Vi+Vr=Vt Penn ESE370 Fall2013 -- DeHon

Reflection Sanity check with previous Short Matched Open Penn ESE370 Fall2013 -- DeHon

Pulse Travel RC Penn ESE370 Fall2013 -- DeHon

Visualization http://www.williamson-labs.com/xmission.htm Penn ESE370 Fall2013 -- DeHon

Back to Source Penn ESE370 Fall2013 -- DeHon

Back at Source? What happens at source? Depends on how terminated Looks like at sink end Penn ESE370 Fall2013 -- DeHon

R≠Z0 What happens? 75 W termination on 50 W line “Short-Circuit” source? Penn ESE370 Fall2013 -- DeHon

Simulation For these, with direct drive from voltage source Source looks like short circuit (not typical of CMOS) Source cannot be changed Penn ESE370 Fall2013 -- DeHon

50W line, 75W termination Penn ESE370 Fall2013 -- DeHon

Step Response Penn ESE370 Fall2013 -- DeHon

Time Permitting Penn ESE370 Fall2013 -- DeHon

Series Termination What happens here? Penn ESE370 Fall2013 -- DeHon

Simulation Penn ESE370 Fall2013 -- DeHon

Series Termination Rseries = Z0 Initial voltage divider Half voltage pulse down line End of line open circuit sees single transition to full voltage Reflection returns to source and sees termination Rseries = Z0 No further reflections Penn ESE370 Fall2013 -- DeHon

Termination Cases Parallel at Sink Series at Source Pix pix Penn ESE370 Fall2013 -- DeHon

CMOS Driver / Receiver Driver: What does a CMOS driver look like at the source? Id,sat=1200mA/mm @ 45nm Receiver: What does a CMOS inverter look like at the sink? Penn ESE370 Fall2013 -- DeHon

Idea Signal propagate as wave down transmission line Delay linear in wire length Speed Impedance Behavior at end of line depends on termination Both src and sink are “ends” Penn ESE370 Fall2013 -- DeHon

Admin HW8 Thursday Finals 2010—2012 online Good, but maybe too long Lectures Wednesday and Friday Andre out next week (12/9-13) Last office hour tomorrow Spencer topic review Monday Dec. 9th classtime (last day of classes) Penn ESE370 Fall2013 -- DeHon