CHAPTER 10 Introduction to VHDL 10.1 VHDL Description of Combinational Circuits 10.2 VHDL Models for Multiplexers 10.3 VHDL Modules 10.4 Signals and Constants 10.5 Arrays 10.6 VHDL Operators 10.7 Packages and Libraries 10.8 IEEE Standard Logic 10.9 Compilation and Simulation of VHDL Code

Objectives Represent gates and combinational logic by concurrent VHDL statements. 2. Given a set of concurrent VHDL statements, draw the corresponding combinational logic circuit, 3. Write a VHDL module for a combinational circuit. 4. Compile and simulate a VHDL module. 5. Use the basic VHDL operators and understand their order of precedence. 6. Use the VHDL types : bit, bit_vector, Boolean, and integer. Define and use an array-type. 7. Use IEEE Standard Logic. Use std_logic_vectors, together with overloaded operators, to perform arithmetic operations.

Introduction to VHDL Hardware Description Language(HDL) allows a digital system to be designed and debugged at a higher level before implementation VHDL, Verilog VHDL – VHSIC(Very High Speed IC) Hardware Description Language Behavior Level, Data Flow Level, Structural Level

10.1 VHDL Description of Combinational Circuits Fig 10-1. Gate Circuit Concurrent statement – order is not important C<=A and B; E<=C or D; E<=C or D; C<=A and B; signal_name<=expression [after delay];

10.1 VHDL Description of Combinational Circuits Fig 10-2. Inverter with Feedback CLK<= not CLK; Not allowed (run time error) Clk<= NOT clk After 10 NS; and CLK<=not CLK after 10 ns;

10.1 VHDL Description of Combinational Circuits Fig 10-3. Three Gates with a Common Input and Different Delays

10.1 VHDL Description of Combinational Circuits Fig 10-4. Array of AND Gates

10.2 VHDL Models for Multiplexers F<= (not A and I0) or (A and I1); Fig 10-5. 2-to-1 Multiplexer Conditional Signal Assignment signal_name<=expression1 when condition1 else expression2 when condition2 [else expressionN];

10.2 VHDL Models for Multiplexers Fig 10-6. Cascaded 2-to-1 MUXes F<= (not A and not B and I0) or (not A and B and l1) or (A and not B and I2) or (A and B and l3);

10.2 VHDL Models for Multiplexers F<= l0 when A&B = “00” else l1 when A&B = “01” else l2 when A&B = “10” else l3; F<= l0 when A = ‘0’ and B = ‘0’ else l1 when A = ‘0’ and B = ‘1’ else l2 when A = ‘1’ and B = ‘0’ else l3; Fig 10-7. 4-to-1 Multiplexer Selected Signal Assignment Statement

10.2 VHDL Models for Multiplexers Selected Signal Assignment Statement with expression_s select signal_s<= expression1 [after delay-time] when choice1, expression2 [after delay-time] when choice2, … [expression_n [after delay-time] when others];

10.3 VHDL Modules Fig 10-8. VHDL Module with Two Gates entity entity-name is [port(interface-signal=declaration);] end [entity][entity-name];

10.3 VHDL Modules Figure 10-9. VHDL Program Structure Interface signal declaration list-of-interface-signals: mode type [:=initial-value] {; list-of-interface-signals: mode type [: =initial-value]}; Port declaration port(A,B: in integer : = 2; C,D: out bit);

10.3 VHDL Modules Architecture declaration architecture architecture-name of entity-name is [declarations] begin architecture body end [architecture] [architecture-name]; Fig 10-10. Entity Declaration for a Full Adder Module

10.3 VHDL Modules Architecture declaration of full adder architecture Equations of FullAdder is begin --concurrent assignment statements Sum<=X xor Y xor Cin after 10 ns; Cout<=(X and Y) or (X and Cin) or (Y and Cin) after 10 ns; end Equations; Fig 10-11. 4-Bit Binary Adder

10.3 VHDL Modules Fig 10-12. Structural Description of 4-Bit Adder Instantiate four copies of full adder

10.3 VHDL Modules add list A B Co C Ci S -- put these signals on the output list force A 1111 -- set the A inputs to 1111 force B 0001 -- set the B inputs to 0001 force Ci 1 -- set Ci to 1 run 50 ns -- run the simulation for 50 ns force Ci 0 force A 0101 force B 1110 run 50 ns

10.3 VHDL Modules ns delta a b co c ci s 0 +0 0000 0000 0 000 0 0000 0 +0 0000 0000 0 000 0 0000 0 +1 1111 0001 0 000 1 0000 10 +0 1111 0001 0 001 1 1111 20 +0 1111 0001 0 011 1 1101 30 +0 1111 0001 0 111 1 1001 40 +0 1111 0001 1 111 1 0001 50 +0 0101 1110 1 111 0 0001 60 +0 0101 1110 1 110 0 0101 70 +0 0101 1110 1 100 0 0111 80 +0 0101 1110 1 100 0 0011

10.3 VHDL Modules

10.3 VHDL Modules 1111+0001+1=0001 with a carry of 1 (at time =40 ns) and 0101+1110+0=0011 with a carry of 1 (at time =80 ns).

10.3 VHDL Modules- Component Components are within architecture and declared at the beginning of the architecture component component-name port (list-of-interface-signals-and-their-types); end component; label: component-name port map (list-of-actual-signals);

10.4 Signals and Constants signal list_of_signal_names: type_name [constraint] [:= initial_value]; signal A,B,C: bit_vector(3 downto 0):= “1111”; signal E,F: integer range 0 to 15; constant constant_name: type_name [constraint] [:=constant_value]; constant limit : integer := 17; constant delay1 : time := 5 ns; A<=B after delay1;

10.4 Signals and Constants Definition bit ‘0’ or ‘1’ boolean FALSE or TRUE integer an integer in the range –( -1) to + ( -1) (some implementations support a wider range) positive an integer in the range 1 to –1 (positive integers) natural an integer in the range 0 to –1 (positive integers and zero) real floating-point number in the range – 1.0E38 to + 1.0E38 character any legal VHDL character including upper- and lower case letters, digits, and special characters; each printable character must be enclosed in single quotes, e.g.,’d’,’7’,’+’ time an integer with units fs, ps, ns, us, ms, sec, min, or hr

10.4 Signals and Constants type state_type is (S0,S1,S2,S3,S4,S5); signal state : state_type := S1; state <= S3;

10.5 Arrays type SHORT_WORK is array (15 downto 0) of bit; signal DATA_WORD: SHORT_WORK; signal ALT_WORK: SHORT_WORD := “0101010101010101”; constant ONE_WORD: SHORT_WORD := (others =>’1’);

10.5 Arrays type array_type_name is array index_range of element_type; 4 2 3 5 6 7 8 9 10 11 12 type array_type_name is array index_range of element_type; signal array_name: array_type_name[:= initial_values]; type matrix4x3 is array (1 to 4, 1 to 3) of integer; signal matrixA: matrix4x3 :=(1,2,3),(4,5,6,),(7,8,9),(10,11,12)); type intvec is array (natural range <>) of integer; signal intvec5: intvec(1 to 5) := (3,2,6,8,1); type matrix is array (natural range <>, natural range <>) of integer;

10.5 Arrays type bit_vector is array (natural range <>) of bit; type string is array (positive range <>) of character; constant string1: string(1 to 29) := “ This string is 29 characters.” constant A: bit_vector(0 to 5) := “101011”; Fig 10-13. VHDL Description of a ROM

10.6 VHDL Operators VHDL Operators binary logical operators: and or nand nor xor xnor relational operators: = /= < <= > >= shift operators: sll srl sla sra rol ror adding operators: + - & (concatenation) unary sign operators: + - multiplying operators: * / mod rem miscellaneous operators: not abs ** - Parentheses change the precedence : order of evaluation not A or B and not C & D ((not A) or B) and ((not) C & D) If A=5, B=4, C=3, (A>=B) and (B<=C) evaluates to FALSE

10.6 VHDL Operators Fig 10-14. Comparator for Integers A sll 2 is “01010100” (shift left logical, filled with ‘0’) A srl 3 is “00010010” (shift right logical, fileed with ‘0’) A sla 3 is “10101111: (shift left arithmetic, filled with rightmost bit) A sra 2 is “11100101” (shift right arithmetic, filled with leftmost bit) A rol 3 is “10101100” (rotate left) A ror 5 is “10101100” (rotate right) A(7)&A(7)&A(7 downto 2) = ‘1’&’1’&”1000101” = “11100101” - Shift right operation

10.7 Packages and Libraries Package declaration Optional package body package package-name is package delarations end [package][package-name]; package body package-name is package delarations end [package body][package-name]; Bit_pack package has a NOR2 gate (inside CD-ROM attached) component Nor2 port (A1,A2: in bit; Z: out bit); end component; --2-input NOR gate entity Nor2 is port (A1,A2: in bit; Z: out bit); end Nor2; architecture concur of Nor2 is begin Z<=not(A1 or A2) after 10ns; end concur;

10.7 Packages and Libraries To access components and functions within a package, libraray BITLIB; Use BITLIB.bit_pack.all; Use BITLIB.bit_pack.Nor2; Fig 10-15. NOR-NOR Circuit and Structural VHDL Code Using Library Components

10.8 IEEE Standard Logic Fig 10-16. Tri-state Buffer IEEE standard 1164 defines a std_logic type of nine values(U, X, 0, 1, Z,W,L,H, -) Fig 10-16. Tri-state Buffer Fig 10-17. Tri-state Buffers Driving a Bus

10.8 IEEE Standard Logic Fig 10-18. Resolution Function for Two Signals F<=A; F<= not B; library ieee; use ieee.std_logic_1164.all;

10.8 IEEE Standard Logic Figure 10-19. VHDL Code for Binary Adder

10.8 IEEE Standard Logic Figure 10-20. VHDL Code for Bi-Directional I/O Pin

10.9 Compilation and Simulation of VHDL Code Fig 10-21. Compilation, Simulation, and Synthesis of VHDL Code

10.9 Compilation and Simulation of VHDL Code Fig 10-22. Simulation of VHDL Code ns delta A B C D 0 +0 3 +0 3 +1 3 +2 8 +0 0 1 0 1 1 1 0 1 1 0 0 1 1 0 1 1 1 0 1 0