Lab2 Adding IP to a Hardware Design Lab: MicroBlaze

Objectives Add additional IP to a hardware design. Implement the design by utilizing ISE. for EDK 6.3i

SetUp For this lab, you will need a memec design V2MB1000 development board and a serial cable. Connect the included programming cable to the PC parallel port and the V2MB1000 development board . Connect a serial cable between the PC and the DB-9 connector on the board. Attach the included power supply to the board. for EDK 6.3i

Procedure In this lab, you will use the system dialog mode of XPS and the text mode features to add the following IP to an existing processor system. OPB timer and counter for time delay OPB GPIO DIP switches OPB Bus MDM UART MicroBlaze INTC LMB BRAM Cntlr LMB BRAM Cntlr Timer BRAM GPIO PSB GPIO LEDs 7Seg LED for EDK 6.3i My IP GPIO SWs

Opening the Project Create a lab2 folder in the X:\EDKLab\ directory. If you wish to continue with your completed design from lab1 then copy the contents of the lab1 folder into the lab2 folder. 1. 2. 3. 4. for EDK 6.3i

Opening the Project Open XPS, click File → Open Project and browse to the project which is in the directory: X:\EDKLab\lab2, then click system.xmp to open the project. 1. 2. for EDK 6.3i

Add the IP by Using Add/Edit Cores(dialog) Click Project → Add/Edit Cores…(dialog) for EDK 6.3i

Add the IP by Using Add/Edit Cores(dialog) Add/Edit Hardware Platform Specifications dialog, displaying the processor and peripherals included in the system thus far. for EDK 6.3i

Add the IP by Using Add/Edit Cores(dialog) In the right window of the Peripherals tab, select each of the following peripherals by using the CRTL key: opb_gpio opb_timer for EDK 6.3i

Add the IP by Using Add/Edit Cores(dialog) Click <<Add to add the selected peripherals. 2. 1. for EDK 6.3i

Add the IP by Using Add/Edit Cores(dialog) Change the instance names of the opb_gpio and opb_timer peripherals (which you just added) to DIP_Switches_8Bit and delay respectively, by clicking once in the Instance column and typing the new name for each desired peripheral. for EDK 6.3i

Add the IP by Using Add/Edit Cores(dialog) 1. Select the Bus Connections tab and set the bus connections as listed in the following table. Click once in each respective column for the corresponding component. 2. for EDK 6.3i

Add the IP by Using Add/Edit Cores(dialog) Select the Addresses tab and change the base- and high-addresses of the following listed peripherals to the listed values. Click the 套用 button and the 確定 button to accept the settings. 1. 2. for EDK 6.3i

Add the IP by Using Add/Edit Cores(dialog) Click Project  View Block Diagram to view the schematic of the design built so far. Close the schematic view. Delay DIP_Switches_8Bit for EDK 6.3i

Use Add/Edit Cores(dialog) to Add Additional Ports and Connect Them 1. Click Project → Add/Edit Cores (dialog) again so additional ports can be added. Click the Ports tab and type OPB_CLK in the Filter substring or instance field. You will see instances listed; some of the instances will show OPB_CLK as they carry the OPB_CLK port. 2. for EDK 6.3i

Use Add/Edit Cores(dialog) to Add Additional Ports and Connect Them Using the CTRL key, select the OPB_CLK for the following instances and click the button. 1. 3. 2. for EDK 6.3i

Use Add/Edit Cores(dialog) to Add Additional Ports and Connect Them Similarly, add the ports to the peripherals listed below. Change the filter substring to match the names below, or to display all ports, delete the text from the filter string. 1. 3. 2. for EDK 6.3i

Use Add/Edit Cores(dialog) to Add Additional Ports and Connect Them Scroll down in the left window and make changes to the following nets. Note: These changes are necessary to ensure all peripherals are driven by the same clock. Original Net Name New Net Name for EDK 6.3i

Use Add/Edit Cores(dialog) to Add Additional Ports and Connect Them Click the net name field of the Interrupt port of the delay instance and make it blank by deleting the default net name. Note: Because this is an output node, it can be left floating if it is not used. At this stage, you will keep it floating; however, in a later lab, you will connect it. for EDK 6.3i

Use Add/Edit Cores(dialog) to Add Additional Ports and Connect Them Right click the GPIO_in port of the DIP_Switches_8Bit, then select Make Signal External. Add Range [0:7] to DIP_Switches_8Bit_in in the up window. 1. 2. for EDK 6.3i

Use Add/Edit Cores(dialog) to Add Additional Ports and Connect Them 1. Select the Parameters tab, in the Choose IP Instance for a list of parameters field, click the drop-down box and select delay as the instance, which will show the available configuration parameters for that instance. 2. for EDK 6.3i

Use Add/Edit Cores(dialog) to Add Additional Ports and Connect Them Select all of the following parameters related to the delay instance and click the Add button to add those parameters with the default values. Change the C_ONE_TIMER_ONLY value from 0 to 1 as you will use only one timer. 1. 3. 2. for EDK 6.3i

Use Add/Edit Cores(dialog) to Add Additional Ports and Connect Them In the Choose IP Instance for a list of parameters field, select DIP_Switches_8bit as the instance, which will show the available configuration parameters for that instance. Select the following parameters and click the Add button to add those parameters. 2. 1. for EDK 6.3i

Use Add/Edit Cores(dialog) to Add Additional Ports and Connect Them Change the default values of the following parameters to the new value provided below. Click the 確定 button to accept the changes. for EDK 6.3i

Edit the MHS File Double-click the MHS File: system.mhs entry under the Project Files in the System tab. for EDK 6.3i

Edit the MHS File Rename the net connected to the delay instance’s OPB_CLK port to sys_clk_s. Save the system.mhs file and then close it. for EDK 6.3i

Edit the MHS File We perform this task here simply to demonstrate that the text file that represents the system can be hand edited if desired. The same result could have been achieved within Add/Edit Cores (dialog) ports tab. for EDK 6.3i

Edit the MHS File Click Project → View Block Diagram to view the schematic of the design. Close the Schematic viewer for EDK 6.3i

Add Pin Assignments for I/O Signals Select the System tab double click on the UCF file. for EDK 6.3i

Add Pin Assignments for I/O Signals Add the following lines to the UCF file. Net DIP_Switches_8Bit_GPIO_in<0> LOC=C6; Net DIP_Switches_8Bit_GPIO_in<0> PULLUP; Net DIP_Switches_8Bit_GPIO_in<1> LOC=D6; Net DIP_Switches_8Bit_GPIO_in<1> PULLUP; Net DIP_Switches_8Bit_GPIO_in<2> LOC=A5; Net DIP_Switches_8Bit_GPIO_in<2> PULLUP; Net DIP_Switches_8Bit_GPIO_in<3> LOC=B5; Net DIP_Switches_8Bit_GPIO_in<3> PULLUP; Net DIP_Switches_8Bit_GPIO_in<4> LOC=C5; Net DIP_Switches_8Bit_GPIO_in<4> PULLUP; Net DIP_Switches_8Bit_GPIO_in<5> LOC=C4; Net DIP_Switches_8Bit_GPIO_in<5> PULLUP; Net DIP_Switches_8Bit_GPIO_in<6> LOC=A4; Net DIP_Switches_8Bit_GPIO_in<6> PULLUP; Net DIP_Switches_8Bit_GPIO_in<7> LOC=B4; Net DIP_Switches_8Bit_GPIO_in<7> PULLUP; for EDK 6.3i

Add Pin Assignments for I/O Signals Save the system.ucf file and then close it. for EDK 6.3i

Creating a Project Navigator Project In XPS, click Options → Project Options, this will open the Project Options dialog. for EDK 6.3i

Creating a Project Navigator Project Select the Hierarchy and Flow tab, Configure the dialog to match the options selected shown below, which should only involve selecting the ISE (ProjNav) radio button. A default ProjNav directory has already been chosen. Click 確定 to close the dialog and apply the settings. 1. 2. 3. for EDK 6.3i

Creating a Project Navigator Project Select Tools  Generate Netlist or click in the toolbar. for EDK 6.3i

Creating a Project Navigator Project Once PlatGen has completed, click Tools → Export to ProjNav. This will create the Project Navigator project and add the appropriate files. Close the project in XPS. for EDK 6.3i

Implement the Design in the Project Navigator Double-click system.npl file in Windows Explorer to open the Project Navigator project located in the lab2\projnav directory. Your project should match follow figure. for EDK 6.3i

Implement the Design in the Project Navigator Toggle the paths in the Sources in Project window to make the paths relative rather than absolute. This promotes portability of the project into a different directory structure. Click on one of the sources in the window and select Toggle Paths. for EDK 6.3i

Implement the Design in the Project Navigator Add the UCF file to the project. Click Project → Add Source and add the system.ucf from the ..\data directory. 1. 2. 3. for EDK 6.3i 4.

Implement the Design in the Project Navigator In ISE, click Edit  Preferences Select the Processes Tab, select Advanced, and click OK. 2. 3. 1. 4. for EDK 6.3i

Implement the Design in the Project Navigator In the Sources in Project window, select system. In the Processes for Source: “system” window, Right-click Implement Design and select Properties. 1. 2. for EDK 6.3i

Implement the Design in the Project Navigator Select the Translate Properties tab and verify that the macro search path is set to ..\implementation. Click OK 1. 2. 3. 4. for EDK 6.3i

Implement the Design in the Project Navigator Select system in the Module view and double-click Implement Design in the Process view. for EDK 6.3i

Implement the Design in the Project Navigator Once the Implement Design process is completed, double-click the View/Edit Routed Design(FPGA Editor) under Place & Route to view the implemented design. for EDK 6.3i

Implement the Design in the Project Navigator Close the FPGA Editor after viewing the implemented design. In the Processes for Source: “system” window, Right-click Generate Programming File and select Properties. for EDK 6.3i

Implement the Design in the Project Navigator Select the Startup Options tab and change CCLK to JTAG Clock, then click 確定. 1. 2. 3. for EDK 6.3i

Implement the Design in the Project Navigator Double-click Generate Programming File to create a BIT file. for EDK 6.3i

Implement the Design in the Project Navigator When the Generate Programming File completes, two critical files have been generated: system.bit – Located in the lab2mb\projnav directory, this BIT file represents the implemented processor system. system_bd.bmm – Located in the lab2mb\implementation directory, this BMM file contains the location constraints for the BRAM utilized in the processor system. This file is used by Data2BRAM to update the BRAM contents with the processor application code. Close the Project Navigator for EDK 6.3i

Download the Project to the V2MB1000 Development Board In XPS, click Tools  Import from ProjNav. This will bring the results from Project Navigator into the XPS environment. For project portability, it is best to use relative path names. Make sure the path names point to the projnav and implementation directory for BIT file system.bit and the BMM file system_bd.bmm respectively. Select OK. 1. 2. 3. for EDK 6.3i

Edit the C File Double-click the C File: TestApp.c entry under the Project Files in the System tab. 1. 2. for EDK 6.3i

Edit the C File Un comment the xil_printf statements in the code, then add DIP_Swithes_8Bit code and save it. for EDK 6.3i

Download the Project to the V2MB1000 Development Board Open a Hyperterminal session with the baud rate set to 9600. Open 開始→程式集→附屬應用程式→通訊→超級終端機 and select COM1. for EDK 6.3i

Download the Project to the V2MB1000 Development Board 1. Set 流量控制:無, then click 確定. 2. for EDK 6.3i

Download the Project to the V2MB1000 Development Board Click Tools  Download. This will compile the software, merge the HW and SW images, and download the merged bit file to the board. for EDK 6.3i

Download the Project to the V2MB1000 Development Board After the board is programmed, you will see a message on the terminal window. Download is completed! 1 1 Reset 10101010 11110000 for EDK 6.3i

Conclusion XPS can create an MHS file representing the processor system. The system can be configured by using peripheral parameters and by controlling internal and external ports. Once the system has been defined, the processor system netlists can be created. In future labs in this course, you will learn how to add user cores, add software to the system, simulate the design, debug the software, and verify the complete design functionality by using a hardware board. for EDK 6.3i