MODEM REGISTER VERIFICATION

Register Name Register Address (16 – Bit) Test Case ID Purpose Description: Read register and compare with expected value. Address: 0x600 – Expected data: 0x01 Address: 0x602 – Expected data: 0x00 Expected outcome: Time 12.19us -> Register address: 0x600 (mif_addr), Read data: 0x01 (mif_rd_data) Time 15.44us -> Register address: 0x602 (mif_addr), Read data: 0x00 (mif_rd_data) Register Name Register Address (16 – Bit) Test Case ID Purpose MOD_DEVID (RO) 0x600, 0x602 mod_reg_mod_dev_id.c To check if device ID is updated in the register.

Register Name Register Address (16 – Bit) Test Case ID Purpose RSSI_VAL (RO) 0x604 mod_reg_rssi.c To check if measured RSSI value is updated in the register. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Read register and compare with expected value at BT2 side. Address: 0x604 – Expected data: 0xA9 Expected outcome: Time: 13482.7us -> Register Address: 0x604 (mif_addr), Read data: 0xA9 (mif_rd_data)

Understanding: RSSI value is calculated based on AGC gain and average power. AGC gain is calculated based on LNA gain, Block 1 (Mixer) gain, Block 2 (VGA) gain. Since the received signal is attenuated in the channel model, the AGC gain adjusts the received signal to a suitable power level. Calculation: RSSI = AGC Gain – Average Power + 4 AGC Gain = LNA + B1B2= 26+29 = 4F (d’79) (Signal is adjusted to the suitable power level) 2's complement of AGC gain = B1 Incoming signals average power is calculated = 0C RSSI = B1 - 0C +4 = A9

Register Name Register Address (16 – Bit) Test Case ID Purpose Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Write register with value 0x0000 ( BT = 0.5) or 0x0008 (BT = 0.55). Register Name Register Address (16 – Bit) Test Case ID Purpose TXFUNC_CNTL_LW (RW) BT_SEL bit (Bit position – 3) 0x608 mod_reg_txfc_ctrl_bt_sel.c Test if the IUT works with the selected BT product configuration 0 - Configure BT product 0.5 (Default) 1 - Configure BT product 0.55

Case 1: BT = 0.5 (iTxBTsel: 1’b0) Contd.. Case 1: BT = 0.5 (iTxBTsel: 1’b0) Expected outcome: Time: 22.74 us -> Register Address: 0x608 (mif_addr), Write data: 0x0000 (mif_wr_data) Time: 1063.57 us -> Output signal: oCoeffPlusOne1 = wCoeffPlusOne_1

Case 2: BT = 0.55 (iTxBTsel = 1’b1) Contd.. Case 2: BT = 0.55 (iTxBTsel = 1’b1) Expected outcome: Time:404.03us -> Register Address: 0x608 (mif_addr), Write enable: 1’b1 (wr_en_signal), Write data: 0x0008 (mif_wr_data) Time:404.10us -> Register Address: 0x608 (mif_addr), Read data: 0x0008 (mif_rd_data) Time: 1063.63 us -> Output signal: oCoeffPlusOne1 = wCoeffPlusOne55_1

BT_SEL = 0.55 BT_SEL = 0.5 Understanding: 1. For BT= 0.5, the pulse shaping the symbol spreads over 2 bit period duration (Time = 377.468us for 1 packet). 2. For BT = 0.55, the symbol spread will be less than 2 bit period duration (Time = 377.343us for 1 packet). We can observe an increase of .125us for BT = 0.5 and decrease in amplitude value. Since the pulse spreads wide. For 1 bit (Bit duration=1us) the bit duration after pulse shaping will be 1.0119785us when BT = 0.5. For 1 bit (Bit duration=1us) the bit duration after pulse shaping will be 1.011643us when BT = 0.55.

Register Name Register Address (16 – Bit) Test Case ID Purpose RXFUNC_CNTL_LW (RW) 1. EL_FULL_PKT_TRK (Bit position – 1) 2. EL_SLOW_TRK_ENB (Bit position – 2) 3. EL_SAMP_ADJ (Bit position – 4) 4. EL_CTRL (Bit position – 5) 5. RSSI_THRESHOLD(Bit position – 15:8) 0x61C mod_reg_el_func_ctrl.c To check early late functionality: EL_FULL_PKT_TRK - Early late tracking for full packet. EL_SLOW_TRK_ENB - Early late slow tracking for payload. EL_SAMP_ADJ - Early late sampling point adjustment. EL_CTRL - Early late sum comparison. RSSI_THRESHOLD - RSSI detection threshold for early late adjustment. Description: Set attenuation value = -85 dBm at BT1 side. Write RXFUNC_CTRL register with value 0x3FCA to enable the above mentioned register bits. Write RXFUNC_CTRL register with value 0x7FFC to disable the above mentioned register bits. Write RSSI_THRESHOLD with value 0x3F and 0x7F to check if the threshold value can be set to all bit range.

Case 1: EL_CTRL and EL_SAMP_ADJ Disabled Contd.. Expected outcome: 1. Time: 1057.97 us -> iElCtrl:1’b0, iElSampAdj:1’b0, wElSumThresMet:1’b1, rSamplAdjFwd:1’b1, rSamplAdjBwd:1’b0 Understanding: EL_CTRL: Controls the Early and Late sum comparison with threshold value. EL_CTRL= 0: When Early sum or Late sum value is greater than the threshold, threshold met signal will be enabled. 2. EL_SAMP_ADJ: Enables/Disables the Early Late Sampling point adjustment based on Early late and matched filter average threshold. EL_SAMP_ADJ =0: Samples will be adjusted based on Early Late threshold condition.(Matched Filter average threshold condition will not be checked).

Case 2: EL_CTRL and EL_SAMP_ADJ Enabled Contd.. Expected outcome: 1. Time: 4798.77 us -> iElCtrl:1’b1, iElSampAdj:1’b1, wElSumThresMet:1’b1, rSamplAdjFwd:1’b1, rSamplAdjBwd:1’b0 Understanding: EL_CTRL: Controls the Early and Late sum comparison with threshold value. EL_CTRL= 1: Both Early sum and Late sum value must be greater than the threshold, threshold met signal will be enabled. 2. EL_SAMP_ADJ: Enables/Disables the Early Late Sampling point adjustment based on Early late and matched filter average threshold. EL_SAMP_ADJ =1: Samples will be adjusted based on Early late threshold met and matched filter average threshold.(Matched Filter average threshold condition will be checked).

Case 1: EL_SLOW_TRK_ENB Enabled Expected outcome: Time: 4857.66us -> iElSLwTrkEnb:1’b1, wElSlwTrkCntrEnb:1’b1, access_match_trig:1’b1 Understanding: EL_SLOW_TRK_ENB: Enables/disables slow tracking EL_SLOW_TRK_ENB =1 , slow tracking will be enabled and samples will be adjusted after Access address match. wSmplAdjBwdSet and wSmplAdjFwdSet are getting set after access address match.

Case 2: EL_SLOW_TRK_ENB Disabled Expected outcome: Time: 1110.60us -> iElSLwTrkEnb:1’b0, wElSlwTrkCntrEnb:1’b0, access_match_trig:1’b1 Understanding: EL_SLOW_TRK_ENB: Enables/disables slow tracking EL_SLOW_TRK_ENB =0 , slow tracking will be disabled and samples are not adjusted after Access address match. wSmplAdjBwdSet and wSmplAdjFwdSet are not getting set after access address match.

Case 1: EL_FULL_PKT_TRK Enabled Expected outcome: Time: 4857.60us -> iElTrkFullEnb:1’b0, access_match_trig:1’b1 Understanding: EL_FULL_PKT_TRK: Enables/disables Full packet tracking EL_FULL_PKT_TRK =0 , full packet tracking will be enabled and samples will be adjusted for payload. wSmplAdjBwdSet and wSmplAdjFwdSet are getting set after access address match.

Case 1: EL_FULL_PKT_TRK Disabled Expected outcome: Time: 11109.60us -> iElTrkFullEnb:1’b1, access_match_trig:1’b1 Understanding: EL_FULL_PKT_TRK: Enables/disables Full packet tracking EL_FULL_PKT_TRK =1 , full packet tracking will be disabled and samples will be adjusted till access address match (not for payload). wSmplAdjBwdSet and wSmplAdjFwdSet are not getting set after access address match.

RSSI_THRESHOLD Functionality Expected outcome: Time: 3539.85us -> iModCntrlRssiThres:7’h0F, rOperVld: 1’b0 -> 1’b1 (Continously Changing), access_match_trig:1’b0 (All packet loss) Time: 4666.60us -> iModCntrlRssiThres:7’h3F, rOperVld: 1’b1, access_match_trig:1’b1(all packet received) Understanding: RSSI_THRESHOLD: RSSI value should be above the configured threshold to enable early late adjustment in the modem. If threshold value is not configured with correct value then Early late adjustment operation will not happen.(Packet loss)

Register Name Register Address (16 – Bit) Test Case ID Purpose Contd.. Description: Set attenuation value = -85 dBm at BT1 side. Write RXFUNC_CTRL register with value 0x3FFF to select the registered input data. Write RXFUNC_CTRL register with value 0x3FBF to select the input data. Register Name Register Address (16 – Bit) Test Case ID Purpose RXFUNC_CNTL_LW (RW) NORM_PH_CTRL (Bit position – 6) 0x61C mod_reg_norm_ph_ctrl.c To check the Normalizer input data selection 0 - Selects the input data 1 - Selects the registered input data

Case 1: NORM_PH_CTRL bit enabled Contd.. Case 1: NORM_PH_CTRL bit enabled Expected outcome: Time:419.50us -> Register Address: 0x61C (mif_addr), Write data: 0x3FFF (mif_wr_data), iNormPhaseCtrl: 1’b1 Time: 534.35 us -> Output signal: wNormInPhase_sel = NormInPhase_q for iNormPhaseCtrl : 1’b1

Case 2: NORM_PH_CTRL bit disabled Contd.. Case 2: NORM_PH_CTRL bit disabled Expected outcome: Time:419.72us -> Register Address: 0x61C (mif_addr), Write data: 0x3FBF (mif_wr_data), iNormPhaseCtrl: 1’b0 Time: 534.28 us -> Output signal: wNormInPhase_sel = iNormInPhase for iNormPhaseCtrl : 1’b0 Understanding: NORM_PH_CTRL: Normalizer input data selection bit. NORM_PH_CTRL = 0, select the incoming input data NORM_PH_CTRL = 1, select the registered input data. To synchronize with the clock.

Register Name Register Address (16 – Bit) Test Case ID Purpose RXFUNC_CNTL_LW (RW) FREQ_CHCK_SUM (Bit position – 7) 0x61C mod_reg_chksum_enb.c To check enabling/disabling of frequency check sum feature 0 - Disable 1 - Enable Description: Set attenuation value = -85 dBm at BT1 side. Write RXFUNC_CTRL register with value 0x3FFF to enable the frequency check sum feature. Write RXFUNC_CTRL register with value 0x3F7F to disable the frequency check sum feature.

Case 1: FREQ_CHCK_SUM bit enabled Expected outcome: Time: 1690.914us -> iFreqCheckSumEnb: 1’b0, wFreqCheckSumFail = 1’b0,wFreqOffs:14’h0000 Time: 1690.976us -> iFreqCheckSumEnb: 1’b0, wFreqCheckSumFail = 1’b1,wFreqOffs:14’h0000 Understanding: FREQ_CHCK_SUM : Enables/disables the frequency check sum feature FREQ_CHCK_SUM = 1, compare the estimated checksum value with threshold value. wFreqCheckSumFail signal will be enabled/disabled based on the comparison. This signal is used to avoid frequency correction when there is false preamble detection. Hence FreqOffs = 0.

Case 2: FREQ_CHCK_SUM bit disabled Expected outcome: Time: 4821.160us -> iFreqCheckSumEnb: 1’b1, wFreqCheckSumFail = 1’b0,wFreqOffs:14’h0007 Time: 4821.226us -> iFreqCheckSumEnb: 1’b1, wFreqCheckSumFail = 1’b0,wFreqOffs:14’h0000 Understanding: FREQ_CHCK_SUM : Enables/disables the frequency check sum feature FREQ_CHCK_SUM = 0, wFreqCheckSumFail will remain low and frequency correction will be carried out even for false preamble detection (FreqOffs = 7)

Register Name Register Address (16 – Bit) Test Case ID Purpose RXFUNC_CNTL_UW (RW) ADJ_CORR_VAL (Bit position – 15:10) 2. DELTA_THRES_VAL (Bit position – 9:0) 0x61E mod_reg_corr_delta_th.c To check read and write operation of adjustment of correlation value from Frequency Offset Estimation module which is sent to Early Late module. To check read and write operation of Delta threshold value which adjusts the Early Late Samples. Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz , Frequency Drift = 100KHz Scenario 1: Write and read RXFUNC_CTRL_UW register with value 0xFFFF (ADJ_CORR_VAL = 0x3F and DELTA_THRES_VAL=0x3FF which is the maximum value for both the bits). Scenario 2: Write and Read RXFUNC_CTRL_UW register with value 0x0001 (ADJ_CORR_VAL = 0x00 and DELTA_THRES_VAL=0x001 which is the minimum value for both the bits).

ADJ_CORR_VAL Functionality Expected outcome: Time:1045.93us -> iAdjCorrVAl:6’h00, oPeakPosi: 6’h0A, iPeakPosiEnb:1’b1, rSampCnt:5’h10 ADJ_CORR_VAL: Correlation value will be adjusted based on the configured value. Configured value will adjust the peak position in Frequency offset estimation module. Adjusted peak position will be used in Early Late module to calculate the sample count which in turn is used to find the symbols.

DELTA_THRES_VAL Functionality Expected outcome and understanding: iDeltaThres:10’h000, (Early – Late ) >= iDeltaThres, more samples will be adjusted since threshold value is very small. iDeltaThres:10’h3FF, (Early – Late ) >= iDeltaThres, less samples will be adjusted since threshold value is very high. No performance degradation.

Register Name Register Address (16 – Bit) Test Case ID Purpose MOD_CNTL_LW (RW) SM_CNTRL (Bit position – 3) 0x624 mod_reg_sm_cntrl_en.c To check the configured bit controls the sleep mode operation from modem MOD_OPER_LW (RW) SM_ENB bit (Bit position – 2) 0x628 To check the configured bit enables/disables the sleep mode operation. Description: Set attenuation value = -85 dBm at BT1 side. Write and read MOD_CNTL_LW register with value 0x0008 to control the sleep mode operation from modem. Write and read MOD_OPER_LW register with value 0x0004 to enable the sleep mode operation. Write and read MOD_OPER_LW register with value 0x0000 to disable the sleep mode operation.

Contd.. Expected outcome: Time = 416.53us -> wREgBankSmCntl:1’b0, wSleepEnb:1’b0, wRxClkEnb:1’b1, wRxSysClkG: 1’b1(ON) Time = 4558.57us -> wREgBankSmCntl:1’b1, wSleepEnb:1’b1, wRxClkEnb:1’b0, wRxSysClkG: 1’b0(OFF) Understanding: When sleep mode operation is enabled Tx and Rx clock will be disabled and device will enter into sleep mode operation (No transmission or reception of packets).

Register Name Register Address (16 – Bit) Test Case ID Purpose Description: Set attenuation value = -85 dBm at BT1 side. Write and read MOD_OPER_LW register with value 0x0008 to enable the dynamic power. Write and read MOD_OPER_LW register with value 0x0000 to disable the dynamic power.. Register Name Register Address (16 – Bit) Test Case ID Purpose MOD_OPER_LW (RW) DYN_PWR_CNTRL (Bit position – 3) 0x628 mod_reg_dyn_pwr_cntrl.c To check the configured bit enables/disables the dynamic power control.

Case 1: DYN_PWR_CNTRL enabled Contd.. Expected outcome: Time = 4668.94us -> wRegBankDynPwrCntl:1’b1, wRxClkEnb: 1’b1, wRxSysClkG:1’b1(ON) Time =5192.67 us -> wRegBankDynPwrCntl:1’b1, wRxClkEnb: 1’b0, wRxSysClkG:1’b1(OFF) Case 2: DYN_PWR_CNTRL disabled Expected outcome: Time = 413.53us -> wRegBankDynPwrCntl:1’b0, wRxClkEnb: 1’b1, wRxSysClkG:1’b1(ON) Time =1048.22us -> wRegBankDynPwrCntl:1’b0, wRxClkEnb: 1’b1, wRxSysClkG:1’b1(ON) Understanding: When dynamic power control is enabled, it will disable the Tx and Rx clock (only when Tx and Rx operation are idle). When dynamic power control is disabled. Tx and Rx clock will be always high even when the Tx and Rx operation are idle.

Register Name Register Address (16 – Bit) Test Case ID Purpose MOD_OPER_LW (RW) RxClkCtrl1 (Bit position – 4) 0x628 mod_reg_rx_clk_cntrl.c To check the configured bit control the clock start stop timing for preamble search module. 0 – Clk ON from RSSI Detection to Access address match 1 – Clk ON during entire RX. Description: Set attenuation value = -85 dBm at BT1 side. Write and read MOD_OPER_LW register with value 0x0000 to enable the clock start stop timing only for Preamble search module.(clock will be on from RSSI detection to Access address match). Write and read MOD_OPER_LW register with value 0x0010 to disable the clock start stop timing for Preamble search module. (clock will be on for entire RX)

Case 1: RxClkCtrl1 disabled Contd.. Expected outcome: Time = 530.97us -> wRegBankRxClkCtrl1:1’b0, rRxClkEnb2: 1’b1, AgcRssiDetPosEdge:1’b1, access_match_trig:1’b0, oModCntrlPreSrchClkG:1’b1(ON) Time =1109.68 us -> wRegBankRxClkCtrl1:1’b0, rRxClkEnb2: 1’b0, AgcRssiDetPosEdge:1’b0, access_match_trig:1’b1, oModCntrlPreSrchClkG:1’b0 (OFF)

Case 2: RxClkCtrl1 enabled Contd.. Case 2: RxClkCtrl1 enabled Expected outcome: Time = 4789.97us -> wRegBankRxClkCtrl1:1’b1, rRxClkEnb2: 1’b1, AgcRssiDetPosEdge:1’b1, access_match_trig:1’b0, oModCntrlPreSrchClkG:1’b1 (ON) Time =4858.66 us -> wRegBankRxClkCtrl1:1’b1, rRxClkEnb2: 1’b1, AgcRssiDetPosEdge:1’b0, access_match_trig:1’b1, oModCntrlPreSrchClkG:1’b1 (ON) Understanding: Clock will be selected based on the configured bit.

Register Name Register Address (16 – Bit) Test Case ID Purpose MOD_OPER_LW (RW) FreqOffClkCtrl (Bit position – 5) 0x628 mod_reg_freq_off_clk_ctrl.c To check the configured bit control the clock start stop timing for frequency offset estimation module. 0 – Clk ON from RSSI Detection to Access address match 1 – Clk ON during entire RX. Description: Set attenuation value = -85 dBm at BT1 side. Write and read MOD_OPER_LW register with value 0x0000 to enable the clock start stop timing only for Frequency offset estimation module.(clock will be on from RSSI detection to Access address match). Write and read MOD_OPER_LW register with value 0x0020 to disable the clock start stop timing for Frequency offset estimation module. (clock will be on for entire RX)

Case 1: FreqOffClkCtrl disabled Contd.. Expected outcome: Time = 530.85us -> wRegBankFreqOffClkCtrl:1’b0, rFreqOffEstClkEnb: 1’b1, AgcRssiDetPosEdge:1’b1, access_match_trig:1’b0, oModCntrlFreqOffEstClkG:1’b1(ON) Time =1109.601 us -> wRegBankFreqOffClkCtrl:1’b0, rFreqOffEstClkEnb: 1’b0, AgcRssiDetPosEdge:1’b0, access_match_trig:1’b1, oModCntrlFreqOffEstClkG:1’b0(OFF)

Case 2: FreqOffClkCtrl enabled Expected outcome: Time = 4789.97us -> wRegBankFreqOffClkCtrl:1’b1, rFreqOffEstClkEnb: 1’b1, AgcRssiDetPosEdge:1’b1, access_match_trig:1’b0, oModCntrlFreqOffEstClkG:1’b1(ON) Time =4863.47us -> wRegBankFreqOffClkCtrl:1’b1, rFreqOffEstClkEnb: 1’b1, AgcRssiDetPosEdge:1’b0, access_match_trig:1’b1, oModCntrlFreqOffEstClkG:1’b1(ON) Understanding: Clock will be selected based on the configured bit.

PreSrch2ClkCtrl (Bit position – 6) Register Name Register Address (16 – Bit) Test Case ID Purpose MOD_OPER_LW (RW) PreSrch2ClkCtrl (Bit position – 6) 0x628 mod_reg_presrch2_clk_ctrl.c To check the configured bit control the clock start stop timing for Preamble Search2 module 0 – Clk ON from RSSI Detection to Preamble Match 1 – Clk ON during entire RX. Description: Set attenuation value = -85 dBm at BT1 side. Write and read MOD_OPER_LW register with value 0x0000 to enable the clock start stop timing only for Preamble search2 module.(clock will be on from RSSI detection to Preamble Match). Write and read MOD_OPER_LW register with value 0x0040 to disable the clock start stop timing for Preamble search2 module. (clock will be on for entire RX)

Case 1: PreSrch2ClkCtrl disabled Expected outcome: Time = 555.85us -> wRegBankPreSrch2ClkCtrl:1’b0, rLrRx2ClkEnb: 1’b1, AgcRssiDetPosEdge:1’b1, iPreMatchedLvl:1’b0, oModCntrlPreSrch2ClkG:1’b1(ON) Time =1104.226us -> wRegBankPreSrch2ClkCtrl:1’b0, rLrRx2ClkEnb: 1’b0, AgcRssiDetPosEdge:1’b0, iPreMatchedLvl:1’b1, oModCntrlPreSrch2ClkG:1’b0(OFF)

Case 2: PreSrch2ClkCtrl enabled Expected outcome: Time = 24156.66us -> wRegBankPreSrch2ClkCtrl:1’b1, rLrRx2ClkEnb: 1’b1, AgcRssiDetPosEdge:1’b1, iPreMatchedLvl:1’b0, oModCntrlPreSrch2ClkG:1’b1(ON) Time =24852.09us -> wRegBankPreSrch2ClkCtrl:1’b1, rLrRx2ClkEnb: 1’b1, AgcRssiDetPosEdge:1’b0, iPreMatchedLvl:1’b1, oModCntrlPreSrch2ClkG:1’b1(ON) Understanding: Clock will be selected based on the configured bit.

Register Name Register Address (16 – Bit) Description Query LR_PREAMB_CONFIG_EXT(RW) LR_PRE_PEAKEARCH_THLD (Bit position –15:0) 0x62C LR Preamble negative/positive detection specific threshold. This threshold is used to detect preamble early and 62 bit correlation preamble This register is used for old Preamble Search Method (Not used in PreambleDetPipeLinedLR). Kindly let us know whether we have to check this functionality. Register Name Register Address (16 – Bit) Description Query AFC_CNTL_UW (RW) PRE_SEARCH_THRESHOLD (Bit position –15:0) 0x632 This indicates the preamble search threshold during correlation. This register is used for old Preamble Search Method during correlation. (Not used in PD1M2M_1stCorrDet). Kindly let us know whether we have to check this functionality.

Register Name Register Address (16 – Bit) Test Case ID Purpose FRQ_DRFT_THSLD_LW (RW) FREQ_DRIFT_THRESHOLD (Bit position –13:0) 0x660 mod_reg_drft_max_limit.c Test if the configured maximum threshold value and limit value qualifies the frequency drift estimation. FRQ_DRFT_THSLD_UW (RW) FREQ_DRIFT_LIMIT_VALUE (Bit position – 13:0) 0x662 Description: Set attenuation value = -85 dBm at BT1 side. Write and read FRQ_DRFT_THSLD_LW register with maximum drift threshold value 0x0064. Write and read FRQ_DRFT_THSLD_UW register with drift limit value 0x0000 to 0x0064. Expected Outcome: Device should receive all the packets when limit value is configured with correct value (depending on the programmed value in channel model). Packet loss can be observed when limit value is not configured with correct value.

Understanding: Maximum drift threshold is the maximum drift allowed which is 100KHz.(Programmed in Channel Model) Limit value is applied whenever the drift estimation exceeds the programmed value (i.e the value in channel model). Case 1: Frequency Drift = 100KHz(Channel model), Maximum Drift Threshold = 0x64, Limit value = 0x64  All packets received Case 2: Frequency Drift = 100KHz(Channel model), Maximum Drift Threshold = 0x00, Limit value = 0x64  All packets received Case 3: Frequency Drift = 100KHz(Channel model), Maximum Drift Threshold = 0x00, Limit value = 0x30  Packet reception is degraded.

Register Name Register Address (16 – Bit) Test Case ID Purpose FRQ_DRFT_CFG_LW(RW) 1. FREQ_DRIFT_CONST_VAL (Bit Position – 15:2) 2. FREQ_DRIFT_CONST_EN (Bit Position – 1) 3. FREQ_DRIFT_EST_EN (Bit Position – 0) 0x664 mod_reg_freq_drift_est.c To check if the configured bit controls the Frequency Drift Estimation operation. Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz, Frequency Drift = 100KHz Write and read FREQ_DRIFT_EST_EN bit with 0x01 to enable the Frequency drift estimation operation. Scenario 1: 1. Write and read FREQ_DRIFT_CONST_EN bit with 0x02 to enable the constant frequency drift estimation and write FREQ_DRIFT_CONST_VAL bit with 0x064 (Depends on the channel model value) constant frequency drift value. 2. Enable ASSERT_DRIFT macro in lec_config.h. (Estimated Drift within ± 10% Tolerance) Scenario 2: 1. Write and read FREQ_DRIFT_CONST_EN bit with 0x00 to enable the actual frequency drift estimation.

Expected Outcome: When FREQ_DRIFT_CONST_EN bit is enabled, output of the Frequency Drift Estimation must be the configured constant value (FREQ_DRIFT_CONST_VAL) (Receive all the packets). When FREQ_DRIFT_CONST_EN bit is disabled, output of the Frequency Drift Estimation is the actual value estimated in the drift estimation module (Receive all the packets). The estimated frequency drift value which is not within the tolerance range will be printed on the console (Assertion should be enabled).

FREQ_DRIFT_SCALING_FACTOR_LRC2 Register Name Register Address (16 – Bit) Test Case ID Purpose FRQ_DRFT_CFG_UW (RW) FREQ_DRIFT_SCALING_FACTOR_UNCODED (Bit Position – 3:0) 0x666 mod_reg_drft_fac_uncoded.c To check if the configured correlation sum average factor (Range 0x00 – 0x0A) qualifies frequency drift estimation for 1M. mod_reg_drft_fac_uncoded_2M.c To check if the configured correlation sum average factor (Range 0x00 – 0x0A) qualifies frequency drift estimation for 2M. FREQ_DRIFT_SCALING_FACTOR_LRC2 (Bit Position – 7:4) mod_reg_drft_fac_coded.c To check if the configured correlation sum average factor (Range 0x00 – 0x0A) qualifies frequency drift estimation for LR-C2. Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz, Frequency Drift = 100KHz Scenario 1: 1. Write and read FRQ_DRFT_CFG_UW register with 0x9044 to select 16(2^4) as the Correlation Sum average factor to estimate the frequency drift . Scenario 2: 1. Write and read FRQ_DRFT_CFG_UW register with 0x90AA to select 1024(2^10) as the Correlation Sum average factor to estimate the frequency drift .

Expected Outcome: Expected Outcome: Applied Frequency Drift = 100KHz, iAvgFactor = 8’h4, Estimated Frequency Drift = 14’h31.(All Packets received) Expected Outcome: Applied Frequency Drift = 100KHz, iAvgFactor = 8’hA, Estimated Frequency Drift = 14’h000.(Packet loss) Understanding: During Frequency Drift estimation, scaling of the calculated correlation sum is performed based on the configured value. 16 samples are used to calculate Correlation sum. Based on the number of samples selected for calculating correlation sum the scaling Factor must be selected.

Register Name Register Address (16 – Bit) Description Query FRQ_DRFT_CFG_UW (RW) FREQ_OFF_EST_ERR_FACTOR (Bit position –14:12) 0x666 Difference of the Frequency Offset error estimate between Middle and Final value should not be more than the configured percentage of the Final estimated value. This percentage is decided by this counter value. Ex: If programmed value is N then (Final – Mid ) < = (Final)/(2^N) The configured bit functionality is based on positive and negative peak which are obtained from Preamble Detection block. Sine the Positive and negative peak values are disabled, functionality of this is not possible to check.

Register Name Register Address (16 – Bit) Test Case ID Purpose FRQ_DRFT_CFG2_LW (RW) LRC8_BOUNDRY_ALIGN_CNTR(Bit position – 8:0) 0x668 mod_reg_boundry_align_cntr_LRC8.c To check if the delay counter is configured with proper value to enable the LR-C8 Frequency Drift Estimation once the 8 bit boundary align pulse is obtained. Description: Set attenuation value = -85 dBm at BT1 side. Set Frequency Offset = 300KHz, Frequency Drift = 100KHz Write and read FRQ_DRFT_CFG2_LW register with 0x130 delay counter value to enable the LRC8 frequency drift estimation.(Value 0x130 because access will match after 304us from first pulse of 8 bit boundary).

Expected Outcome: Time= 1416.85us, iLrC8BndryAlignCntr:9’h130,rPreMatchedSmpCnt:13’h1300, wFreqDrftLrC8EstOn:1’b0 Understanding: Frequency Drift Estimation will start only when the count of samples from the start of preamble match is equal to the configured delay counter .