Reduced Voltage Test Can be Faster!

Slides:

Advertisements

Similar presentations

Weighted Random and Transition Density Patterns for Scan-BIST Farhana Rashid* Vishwani D. Agrawal Auburn University ECE Department, Auburn, Alabama

Advertisements

Leakage and Dynamic Glitch Power Minimization Using MIP for V th Assignment and Path Balancing Yuanlin Lu and Vishwani D. Agrawal Auburn University ECE.

Power Management (Application of Autonomic Computing Concepts) Omer Rana.

Praveen Venkataramani Suraj Sindia Vishwani D. Agrawal FINDING BEST VOLTAGE AND FREQUENCY TO SHORTEN POWER CONSTRAINED TEST TIME 4/29/ ST IEEE VLSI.

Yuanlin Lu Intel Corporation, Folsom, CA Vishwani D. Agrawal

Fall 06, Sep 19, 21 ELEC / Lecture 6 1 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic.

Dynamic SCAN Clock control In BIST Circuits

Dynamic Scan Clock Control In BIST Circuits Priyadharshini Shanmugasundaram Vishwani D. Agrawal

Energy Source Lifetime Optimization for a Digital System through Power Management Department of Electrical and Computer Engineering Auburn University,

Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock Priyadharshini Shanmugasundaram Vishwani D. Agrawal.

Timing Analysis Timing Analysis Instructor: Dr. Vishwani D. Agrawal ELEC 7770 Advanced VLSI Design Team Project.

Spring 07, Feb 20 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Reducing Power through Multicore Parallelism Vishwani.

A Tutorial on Battery Simulation - Matching Power Source to Electronic System Manish Kulkarni and Vishwani D. Agrawal Auburn University Auburn, AL 36849,

8/19/04ELEC / ELEC / Advanced Topics in Electrical Engineering Designing VLSI for Low-Power and Self-Test Fall 2004 Vishwani.

Priyadharshini Shanmugasundaram Vishwani D. Agrawal DYNAMIC SCAN CLOCK CONTROL FOR TEST TIME REDUCTION MAINTAINING.

9/20/05ELEC / Lecture 81 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

Spring 08, Feb 28 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Retiming Vishwani D. Agrawal James J. Danaher.

8/18/05ELEC / Lecture 11 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

Institute of Digital and Computer Systems 1 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Chapter 5 Finding Peak Performance in a Process.

May 28, 2003Minimum Dynamic Power CMOS1 Minimum Dynamic Power CMOS Circuits Vishwani D. Agrawal Rutgers University, Dept. of ECE Piscataway, NJ 08854

HIGH-SPEED VLSI TESTING WITH SLOW TEST EQUIPMENT Vishwani D. Agrawal Agere Systems Processor Architectures and Compilers Research Murray Hill, NJ

2/8/06D&T Seminar1 Multi-Core Parallelism for Low- Power Design Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 13: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.

Spring 07, Apr 5 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Retiming Vishwani D. Agrawal James J. Danaher Professor.

Spring 07, Feb 22 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Power Aware Microprocessors Vishwani D. Agrawal.

Architectural Power Management for High Leakage Technologies Department of Electrical and Computer Engineering Auburn University, Auburn, AL /15/2011.

Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 11 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Adiabatic Logic Vishwani D. Agrawal.

By Praveen Venkataramani Vishwani D. Agrawal TEST PROGRAMMING FOR POWER CONSTRAINED DEVICES 5/9/201322ND IEEE NORTH ATLANTIC TEST WORKSHOP 1.

By Praveen Venkataramani Committee Prof. Vishwani D. Agrawal (Advisor) Prof. Adit D. Singh Prof. Fa Foster Dai REDUCING ATE TEST TIME BY VOLTAGE AND FREQUENCY.

Power-Aware SoC Test Optimization through Dynamic Voltage and Frequency Scaling Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal Dept. of Electrical.

ELEC 6270 Low power design of Electronic Circuits Advisor: Dr.Vishwani Agrawal Student: Chaitanya Bandi.

Copyright Agrawal, 2011ELEC5270/6270 Spr 15, Lecture 71 ELEC 5270/6270 Spring 2015 Low-Power Design of Electronic Circuits Energy Source Design Vishwani.

Jia Yao and Vishwani D. Agrawal Department of Electrical and Computer Engineering Auburn University Auburn, AL 36830, USA Dual-Threshold Design of Sub-Threshold.

Low Power Architecture and Implementation of Multicore Design Khushboo Sheth, Kyungseok Kim Fan Wang, Siddharth Dantu ELEC6270 Low Power Design of Electronic.

Optimal Selection of ATE Frequencies for Test Time Reduction Using Aperiodic Clock Sindhu Gunasekar Vishwani D. Agrawal.

PRAVEEN VENKATARAMANI VISHWANI D. AGRAWAL Auburn University, Dept. of ECE Auburn, AL 36849, USA 26 th International.

Low Power – High Speed MCML Circuits (II)

26 th International Conference on VLSI January 2013 Pune,India Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages Vijay.

Robust Low Power VLSI ECE 7502 S2015 Minimum Supply Voltage and Very- Low-Voltage Testing ECE 7502 Class Discussion Elena Weinberg Thursday, April 16,

A Test Time Theorem and Its Applications Praveen Venkataraman i Suraj Sindia Vishwani D. Agrawal

VLSI Design & Embedded Systems Conference January 2015 Bengaluru, India Few Good Frequencies for Power-Constrained Test Sindhu Gunasekar and Vishwani D.

DPPM for Analog and RF Circuits Vishwani D. Agrawal Auburn University, Auburn, AL 36849, USA Suraj Sindia Intel Corporation, Hillsboro,

-1- UC San Diego / VLSI CAD Laboratory Optimization of Overdrive Signoff Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li and Siddhartha Nath Tuck-Boon Chan,

11/15/05ELEC / Lecture 191 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

Power Problems in VLSI Circuit Testing Keynote Talk Vishwani D. Agrawal James J. Danaher Professor Electrical and Computer Engineering Auburn University,

ELEC Digital Logic Circuits Fall 2015 Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering.

Characterizing Processors for Energy and Performance Management Harshit Goyal and Vishwani D. Agrawal Department of Electrical and Computer Engineering,

Department of Electrical and Computer Engineering Auburn University, AL USA.

Very low voltage 16-bit counter in high leakage static CMOS technology

Estimate power saving by clock slowdown for s5378 in 180nm and 32nm CMOS Chao Han ELEC 6270.

Vishwani D. Agrawal James J. Danaher Professor

Circuits and Interconnects In Aggressively Scaled CMOS

Power-Aware System-On-Chip Test Optimization

Vishwani D. Agrawal James J. Danaher Professor

332:479 Concepts in VLSI Design Lecture 24 Power Estimation

CSV881: Low-Power Design Multicore Design for Low Power

ELEC 7770 Advanced VLSI Design Spring 2010 Interconnects and Crosstalk

Dual Mode Logic An approach for high speed and energy efficient design

Vishwani D. Agrawal James J. Danaher Professor

Vishwani D. Agrawal James J. Danaher Professor

ELEC 5270/6270 Spring 2011 Low-Power Design of Electronic Circuits Pass Transistor Logic: A Low Power Logic Family Vishwani D. Agrawal James J. Danaher.

Vishwani D. Agrawal James J. Danaher Professor

Pre-Computed Asynchronous Scan Invited Talk

CSV881: Low-Power Design Gate-Level Power Optimization

CSV881: Low-Power Design Power-Constrained Testing

Energy Efficient Power Distribution on Many-Core SoC

Testing in the Fourth Dimension

500 nm WRITE VOLTAGE 0 V.

Towards a Fully Digital State-of-the-art Analog SiPM

ELEC 7770 Advanced VLSI Design Spring 2012 Gate Sizing

Presentation transcript:

Reduced Voltage Test Can be Faster! Vishwani D. Agrawal vagrawal@eng.auburn.edu Support from NSF Grant 1116213 11/7/2012 ITC '12: Elevator Talk

Effects of Reducing Supply Voltage Critical path slows down. Power reduces as V2. Test produces more than functional activity; consumes more power that the circuit is designed for. Test clock is slower due to power constrain. 11/7/2012 ITC '12: Elevator Talk

Power and Frequency vs. Voltage Structure constrained test Power constrained test Max. clock frequency (structure constrained) Peak power/cycle during test PMAXfunc Vtest Nominal voltage Voltage VDD 11/7/2012 ITC '12: Elevator Talk

Reduced Voltage Test Results Circuit (180nm CMOS) PMAX per cycle (mW) 1.8V test freq. (MHz) Test voltage (volts) Test clock freq. (MHz) Test time reduction (%) s298 1.2 187 1.08 500 62.5 s13207 21.3 110 1.45 165 40.3 s38584 110.6 129 1.50 31.0 P. Venkataramani and V. D. Agrawal, “Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage,” Proc. 26th International Conf. VLSI Design, January 2013. 11/7/2012 ITC '12: Elevator Talk