Day 19: October 24, 2011 Ratioed Logic ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 19: October 24, 2011 Ratioed Logic Penn ESE370 Fall2011 -- DeHon

Previously Restoration and Noise Margins CMOS Gates Drive rail-to-rail Only one transistor turned on in steady state Only subthreshold current in steady state Penn ESE370 Fall2011 -- DeHon

Today Ratioed Gates Correctness Performance Power Implications Penn ESE370 Fall2011 -- DeHon

Note on what about to see Not clear win Should be able to analyze Chance to exercise analysis Kind of thing you want to be able to analyze Pattern should recognize Stepping stone to more interesting things to come… Penn ESE370 Fall2011 -- DeHon

Idea Building both pull-up and pull-down can be expensive – many gates Seems wasteful to build logic function twice Once in pullup, once in pulldown Large capacitance Penn ESE370 Fall2011 -- DeHon

Idea Maybe only need to build one Build NFET pulldown Exploit high N mobility traditional Penn ESE370 Fall2011 -- DeHon

Ratioed Inverter Does this work? Vout for Vin=0V ? Vout for Vin=1V ? WP=1 WN=1 Penn ESE370 Fall2011 -- DeHon

Ratioed Inverter Does this work? Vout for Vin=0V ? Vout for Vin=1V ? WP=1 WN=1 Penn ESE370 Fall2011 -- DeHon

Ratioed Inverter Wn=1 Penn ESE370 Fall2011 -- DeHon

Ratioed Inverter How do we need to size N to make it work? WP=1 Penn ESE370 Fall2011 -- DeHon

DC Transfer Function Penn ESE370 Fall2011 -- DeHon

Ratioed Inverter How do we need to size P to make it work? WN=1 Penn ESE370 Fall2011 -- DeHon

P vs. N Conclude: still prefer N to P for ratioed logic ….at least for now Penn ESE370 Fall2011 -- DeHon

Worst-Case Output Drive Strength? Rdrive? WP=1 Penn ESE370 Fall2011 -- DeHon

Noise Margin Tradeoff What is impact of increasing (reducing) noise margin? Penn ESE370 Fall2011 -- DeHon

Ratioed Inverter Sizing Penn ESE370 Fall2011 -- DeHon

Ratioed Inverter Sizing What causes knee in curve at high end? Penn ESE370 Fall2011 -- DeHon

Size for R0/2 drive? How do we size for R0/2 drive? Penn ESE370 Fall2011 -- DeHon

Compare Static CMOS For Rdrive=R0/2 inverter Total Transistor Width? Input capacitance load? Penn ESE370 Fall2011 -- DeHon

Power? Istatic ? Output high? Output low? Ileak Ipmos_on Vdd/(R0/2) -- for our sample case Penn ESE370 Fall2011 -- DeHon

Power Ptot ≈ a(½Cload+Csc)V2f +PlowV2/Rpon +(1-Plow)VI’s(W/L)e-Vt/(nkT/q) Penn ESE370 Fall2011 -- DeHon

How size for R0/2 drive? Penn ESE370 Fall2011 -- DeHon

How size for R0/2 drive? Penn ESE370 Fall2011 -- DeHon

Which Implementation is faster in ratioed logic? Penn ESE370 Fall2011 -- DeHon

Illustrates Preferred gate changes Penn ESE370 Fall2011 -- DeHon

How size for R0/2 drive? How size K-input nor? Penn ESE370 Fall2011 -- DeHon

When better than CMOS nor-k? Better = smaller, lower input capacitance Penn ESE370 Fall2011 -- DeHon

Energy vs. Power? Which do we care about? Battery operated devices? Desktops? Pay for energy by kW-Hr? Penn ESE370 Fall2011 -- DeHon

Admin Project Should have read it Built and simulated baseline? Do it by Wednesday Started list of optimizations to try? If don’t have list by Wed, talk with Paul… Penn ESE370 Fall2011 -- DeHon

Ideas There are other logic disciplines We have the tools to analyze Ratioed Logic Tradeoff noise margin for Reduced area? Capacitive load? Dissipates static power in one mode Penn ESE370 Fall2011 -- DeHon