Overview: Fault Diagnosis

Slides:



Advertisements
Similar presentations
Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Design Representation and Fault Detection
Advertisements

Random Testing Tor Stålhane Jonas G. Brustad. What is random testing The principle of random testing is simple and can be described as follows: 1.For.
10/28/2009VLSI Design & Test Seminar1 Diagnostic Tests and Full- Response Fault Dictionary Vishwani D. Agrawal ECE Dept., Auburn University Auburn, AL.
1 Dictionary-Less Defect Diagnosis as Surrogate Single Stuck-At Faults Chidambaram Alagappan Vishwani D. Agrawal Department of Electrical and Computer.
4/28/05Ray: ELEC Fault Diagnosis Using Fault Dictionaries and Probability Adam Ray April 28, 2005.
Compaction of Diagnostic Test Set for a Full-Response Dictionary Mohammed Ashfaq Shukoor Vishwani D. Agrawal 18th IEEE North Atlantic Test Workshop, 2009.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 71 Lecture 7 Fault Simulation n Problem and motivation n Fault simulation algorithms n Serial n Parallel.
Designing Oracles for Grover Algorithm
Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4b1 Design for Testability Theory and Practice Lecture 4b: Fault Simulation n Problem and motivation.
4/20/2006ELEC7250: Alexander 1 LOGIC SIMULATION AND FAULT DIAGNOSIS BY JINS DAVIS ALEXANDER ELEC 7250 PRESENTATION.
Lecture 5 Fault Simulation
Chapter 4 Gates and Circuits.
10/25/2007 ITC-07 Paper Delay Fault Simulation with Bounded Gate Delay Model Soumitra Bose Design Technology, Intel Corp. Folsom, CA Hillary.
Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Fault Simulation Vishwani D. Agrawal James J.
25/06/2015Marius Mikucionis, AAU SSE1/22 Principles and Methods of Testing Finite State Machines – A Survey David Lee, Senior Member, IEEE and Mihalis.
4/26/05Cheng: ELEC72501 A New Method for Diagnosing Multiple Stuck- at-Faults using Multiple and Single Fault Simulations An-jen Cheng ECE Dept. Auburn.
Technical University Tallinn, ESTONIA Overview: Fault Simulation Overview about methods Low (gate) level methods Parallel fault simulation Deductive fault.
Unit II Test Generation
Technical University Tallinn, ESTONIA 1 Boolean derivatives Calculation of the Boolean derivative: Given:
Unit V Fault Diagnosis.
Technical University Tallinn, ESTONIA 1 Faults in Circuits and Fault Diagnosis 0110 T FaultF 5 located Fault table Test experiment Test generation.
ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTEMS
CAS 721 Course Project Minimum Weighted Clique Cover of Test Set By Wei He ( )
Operational Research & ManagementOperations Scheduling Economic Lot Scheduling 1.Summary Machine Scheduling 2.ELSP (one item, multiple items) 3.Arbitrary.
An introduction to Fault Detection in Logic Circuits By Dr. Amin Danial Asham.
2. Sissejuhatus teooriasse
Abdul-Rahman Elshafei – ID  Introduction  SLAT & iSTAT  Multiplet Scoring  Matching Passing Tests  Matching Complex Failures  Multiplet.
Manufacture Testing of Digital Circuits
Technical University Tallinn, ESTONIA Overview: Fault Simulation Overview about methods Low (gate) level methods Parallel fault simulation Deductive fault.
Copyright 2001, Agrawal & BushnellLecture 6:Fault Simulation1 VLSI Testing Lecture 6: Fault Simulation Dr. Vishwani D. Agrawal James J. Danaher Professor.
Fault Models, Fault Simulation and Test Generation Vishwani D. Agrawal Department of ECE, Auburn University Auburn, AL 36849, USA
COE-571 Digital System Testing A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries Authors: P. Bernardi, M. Grosso, M. Rebaudengo,
Technical University Tallinn, ESTONIA Overview: Fault Simulation Overview about methods Low (gate) level methods Parallel fault simulation Deductive fault.
Reducing Structural Bias in Technology Mapping
Today’s Lecture Neural networks Training
Self-Checking Circuits
Faults in Circuits and Fault Diagnosis
Overview Part 2 – Combinational Logic Functions and functional blocks
Finite state machine optimization
Finite state machine optimization
Fault Diagnosis.
The minimum cost flow problem
SLIDES FOR CHAPTER 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
Generalization of BDDs
VLSI Testing Lecture 6: Fault Simulation
Algorithms and representations Structural vs. functional test
VLSI Testing Lecture 14: Built-In Self-Test
Lecture 7 Fault Simulation
ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES
Chapter 5. Optimal Matchings
VLSI Testing Lecture 6: Fault Simulation
Defect and High Level Fault Modeling in Digital Systems
KU College of Engineering Elec 204: Digital Systems Design
LPSAT: A Unified Approach to RTL Satisfiability
Automatic Test Generation for Combinational Circuits
VLSI Testing Lecture 8: Sequential ATPG
KU College of Engineering Elec 204: Digital Systems Design
Automatic Test Pattern Generation
Topics Switch networks. Combinational testing..
UNIVERSITY OF MASSACHUSETTS Dept
Improvements in FPGA Technology Mapping
Algorithms (2IL15) – Lecture 7
VLSI Testing Lecture 7: Delay Test
UNIVERSITY OF MASSACHUSETTS Dept
Sungho Kang Yonsei University
Lecture 26 Logic BIST Architectures
ECE 352 Digital System Fundamentals
ECE 352 Digital System Fundamentals
Lecture 13 Sequential Circuit ATPG Time-Frame Expansion
Presentation transcript:

Overview: Fault Diagnosis Combinational methods of diagnosis Fault table based methods Fault Dictionary based methods Minimization of diagnostic data in fault tables Methods for improving the diagnostic resolution Sequential methods of diagnosis Edge-Pin testing Guided Probe fault location Fault diagnosis with Boolean Differentials Physical Defect Diagnosis Design error diagnosis

Combinational Fault diagnosis Fault localization by fault tables E 1 2 3 F 1 2 3 4 5 6 7 T 1 1 T 1 1 1 6 Fault F located 5 Faults F and F are not distinguishable 1 4 No match, diagnosis not possible

Combinational Fault Diagnosis Fault localization by fault dictionaries Fault dictionaries contain the sama data as the fault tables with the difference that the data is reorganised The column bit vectors can be represented by ordered decimal codes or by some kind of compressed signature

Combinational Fault Diagnosis Minimization of diagnostic data To reduce the cost of building a fault table, the detected faults may be dropped from simulation All the faults detected for the first time by the same vector produce the same column vector in the table, and will included in the same equivalence class of faults Testing can stop after the first failing test, no information from the following tests can be used With fault dropping, only 19 faults need to be simulated compared to the all 42 faults The following faults remain not distinguishable: {F2, F3}, {F1, F4}. A tradeoff between computing time and diagnostic resolution can be achieved by dropping faults after k >1 detections

Sequential Fault Diagnosis Sequential fault diagnosis by Edge-Pin Testing Diagnostic tree: Two faults F1,F4 remain indistinguishable Not all test patterns used in the fault table are needed Different faults need for identifying test sequences with different lengths The shortest test contains two patterns, the longest four patterns Questions: 1) How the tree Works if the system is fault-free? 2) What if a real fault is missing in the Fault Table?

Sequential Fault Diagnosis Guided-probe testing at the gate level Searh tree: Faulty circuit Questions: 1) Is the order of measuring of signals X5,2 and X6 important? 2) Need both X5,2 and X6 observation

Optimized Critical Path Tracing with BDDs Property 2: If a test vector X activates in SSBDD a 0-path (1-path) which travers a subset of nodes M, then only 0-nodes (1-nodes) have to be considered as fault candidates Fault diagnosis / Fault simulation: y y Fault diagnosis and fault simulation can be speed-up by using Property 2 Speeding-up simulation: M = {1,2,3,4,6,7} M* = {1,6,7} – by Property 2 M** = {6,7} – by Property 1 Only 6 and 7 have to be considered

About Diagnostic Resolution Fault localization by fault tables E 1 2 3 F 1 2 3 4 5 6 7 T 1 1 T 1 1 1 6 Fault F located 5 Faults F and F are not distinguishable 1 4 No match, diagnosis not possible

About Diagnostic Resolution Fault localization by fault tables F 1 2 3 4 5 6 7 T 1 1 T 1 1 1 6 Which faults are suspected if only T3 fails? Fault F1 can be masked at T2, F2 - at T4, F4 at T2, and F6 – can be masked at both T5 and T6

Single fault assumption Multiple faults allowed Fault Diagnosis Dilemmas Diagnosis method Fault table Test result Devil’s advocate approach Tested faults Passed Failed Single fault assumption Fault candi-dates Diagnosis Multiple faults allowed ? Fault candidates Angel’s advocate Proved OK Fault candidates

Improving Diagnostic Resolution Generating tests to distinguish faults To improve the fault resolution of a given test set T, it is necessary to generate tests to distinguish among faults equivalent under T Consider the problem of distinguishing between faults F1 and F2. A test is to be found which detects one of these faults but not the other The following cases are possible: F1 and F2 do not influence the same outputs A test should be generated for F1 (F2) using only the circuit feeding the outputs influenced by F1 (F2) F1 and F2 influence the same set of outputs. A test should be generated for F1 (F2) without activating F2 (F1) How to activate a fault without activating another one?

Improving Diagnostic Resolution Generating tests to distinguish faults Faults are influencing on different outputs: Method: F1 may influence both outputs, F2 may influence only x8 A test pattern 0010 activates F1 up to the both outputs, and F2 only to x8 If both outputs will be wrong, F1 is present If only x8 will be wrong, F2 is present F1: x3,1  0 x 2 3 4 3,1 3,2 5 6 7 8 1 & F2: x4  1

Improving Diagnostic Resolution Generating tests to distinguish faults How to activate a fault without activating another one? Method: Both faults influence the same output of the circuit One of them should be blocked Two possibilities: A test pattern 0100 activates the fault F2. F1 is not activated: the line x3,2 has the same value as it would have if F1 were present A test pattern 0110 activates the fault F2. F1 is now activated at his site but not propagated through the AND gate x 5,1 5,2 2 3 4 3,1 3,2 5 6 7 8 1 & 0/1 F1: x3,2  0 F2: x5,2  1

Improving Diagnostic Resolution Generating tests to distinguish faults How to activate a fault without activating another one? Method: Both of the faults may influence only the same output Both of the faults are activated to the same OR gate, none of them is blocked However, the faults produce different values at the inputs of the gate, they are distinguished if x8 = 0, F1 is present otherwise, if x8 = 1 (OK value) either F2 is present or none of the faults are present F1: x3,1  1 1 x 1 x 1 7 x x x 2 5 5,1 1 x 5,2 x x 3,1 1 x 3 x 8 3,2 x 6 & x 4 1 F2: x3,2  1

Calculation of Diagnostic Resolution Block-Level System Network Diagnostic matrix Diagnosability measure B Tests T1 T2 T3 T4 1 2 3 4 5 6 7 8 9 10 11 D = 1.57 Testability based partitioning of blocks: M = {{s1},{s2},{s3,s6,s9},{s4,s7},{s5,s8},{s10},{s11}}

Random Generation of Diagnostic Tests The main idea of the test generation method is to organize the test pattern selection process so that in each step the next test pattern is selected from a package of randomly generated patterns, which detects less or equal number of new not yet detected faults compared to the given criterion. The algorithm can work as follows: Criterion  is defined A first pattern is selected which detects as less as possible faults Each next pattern is selected so that the number of new not yet detected faults were minimum for the current set of randomly generated patterns, and is less than  If such patterns can not be found the criterion  will be increased The procedure will finish when the number of unsuccessful trials will reach the predetermined criterion (value) Fault coverage 

Random Generation of Diagnostic Tests Fault coverage 100% 1 The criterion 1 is equal to the min number of detectable faults. The probability of high average increment is big. Fault coverage is increasing fast, but the average diagnostic resolution remains bad (big average number of undistinguishable faults). The test length will be small. Fault coverage < 100% 2 The criterion 2 is defined starting from 1 and will work only after fixing the first test pattern. The probability of high average increment is as low or less as the criterion. Fault coverage is increasing slowly, but this is not the goal. The average diagnostic resolution will be very good (small average number of undistinguishable faults). The length of the test will be big, but this is the normal cost of reaching the goal – good fault resolution.

Boolean Differentials and Fault Diagnosis dx - fault variable, dx  (0,1) dx = 1, if the value of x has changed because of a fault Partial Boolean differential (for fault simulation): Full Boolean differential (for fault diagnosis):

Boolean Differentials and Fault Diagnosis Diagnostic experiment: Substitution of values: x1 = 0 x2 = 1 x3 = 1 dy = 0 Test pattern - Correct reaction Adjusting for SAF faults: Partial diagnosis:

Boolean Differentials and Fault Diagnosis 1) Correct output signal: x1 = 0 x2 = 0 x3 = 0 dy = 1 Two diagnostic experiments: x1 = 0 x2 = 1 x3 = 1 dy = 0 2) Erroneous output signal: Diagnosis from two experiments:

Boolean Differentials and Fault Diagnosis Diagnosis from two experiments: Rule: = 0 Rule: Final diagnosis: The line x3 works correctly There is a fault: The fault is missing Question: 1) Which question regarding the possible present faults is still open?

Correctness Proof with Test Pairs We will test the fault x11 The test is successful So, we conclude that x1 is correct & 1 x1 x2 x3 y x10 Let us use now mathematics: Now we are not any more very sure about x1

Correctness Proof with Test Pairs & 1 x1 x2 x3 y x10 We have: 2. test: we change the value of x1 to have a test pair & 1 x1 x2 x3 y x10 Both experiments together:

Diagnostic model: Full diferential equation Diagnostic Equation Digital circuit: X y=F(X) y dy X,dX dy=F(X,dX) Diagnostic model: Full diferential equation X dy F(X) dX Test Test result Fault(s) Function Digital system Diagnostic equation: F(X,dX) = dy

How the Test Tasks are Related Test result Diagnostic equation: Digital system X F(X,dX) = dy F(X) dy dX Test Test result Function Fault(s) Fault list Task Given Find Test generation dx dy = 1 X Fault diagnosis dy {dx} Fault simulation Special case of fault diagnosis Both equations can be presented as SAT tasks