Chapter 6 (II) Designing Combinational Logic Circuits (II) EE141 Chapter 6 (II) Designing Combinational Logic Circuits (II) Dynamic CMOS Logic V1.0 5/4/2003 V1.1 5/11/2003 V1.2 5/15/2003

Revision Chronicle 5/4: 5/11: Split Chapter 6 into two parts: Part I focuses on Static and Pass Transistor Logic. Part II focuses on Dynamic Logic 5/11: Make minor revision in figures and adding the summary. Make minor revision in figures and equations

EE141 Dynamic CMOS In Static CMOS circuits, at every point in time (except when switching), the output is connected to either GND or VDD via a low resistance path. Fan-in of n requires 2n (n NMOS plus n PMOS) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. Requires on n + 2 (n+1 NMOS plus 1 PMOS) transistors

Basic Dynamic Gate Clk Clk Out Out CL In1 A In2 PDN PDN C In3 B Clk EE141 Basic Dynamic Gate Mp Clk Clk Mp Out Out CL In1 A In2 PDN PDN C In3 B Clk Me Clk Me For class handout

Two Phase Operations Precharge (Clk = 0) Evaluate (Clk = 1) off Clk EE141 Two Phase Operations off Clk Clk Mp Mp on 1 Out Out CL AB+C In1 A In2 PDN C In3 B Clk Me off Clk Me on For lecture Evaluate transistor, Me, eliminates static power consumption Precharge (Clk = 0) Evaluate (Clk = 1)

EE141 Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation (one chance only). Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during the evaluation phase (PDN off), state is stored on CL This behavior is fundamentally different than the static counterpart that always has a low resistance path between the output and one of the power rails. Different from Static CMOS  Output is connected to Either Vdd or GND through low-resistance path.

Properties of Dynamic Gates (I) EE141 Properties of Dynamic Gates (I) Logic function is implemented by the PDN only Number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed: Sizing of the devices does not affect the logic levels (c.f., Pseudo NMOS) Faster switching speeds Reduced load capacitance due to reduced Logical Effort (Cin) Reduced load capacitance due to smaller internal capacitance. No short-circuit current, Isc, so all the current provided by PDN goes into discharging CL CL being lower also contributes to power savings

Properties of Dynamic Gates (II) EE141 Properties of Dynamic Gates (II) Power Dissipation No static current path ever exists between VDD and GND (including Psc) No glitching Higher transition probabilities: Extra loading on CLK Overall power dissipation usually higher than static CMOS PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL are equal to VTn Low noise margin (NML) Needs a precharge/evaluate clock (CLK) tPLH = 0, tPHL = Function of CL and PDN

Charge Leakage and (3): Reversed-biased diode EE141 Charge Leakage leakage sources are reverse-biased diode and the sub-threshold leakage of the NMOS pulldown device. Charge stored on CL will leak away with time (input in low state during evaluation) Requires a minimum clock rate - so not good for low performance products such as watches (or when have conditional clocks) PMOS precharge device also contributes some leakage due to reverse bias diode and subthreshold conduction that, to some extent, offsets the leakage due to the pull down paths. and (3): Reversed-biased diode and (4): Subthreshold leakage current (dominated)

Charge Leakage Need minimum clock rate up to a few kHz Not good for low-performance applications such as watches, etc.

Solution to Charge Leakage EE141 Solution to Charge Leakage Adding Bleeder Transistor: Same approach as level restorer for pass-transistor logic. The Bleeder transistor is made high (device is small) A “feedback” configuration to elimaite static power consumption During precharge, Out is VDD and inverter out is GND, so keeper is on During evaluation if PDN is off, the keeper compensates for drained charge due to leakage. If PDN is on, there is a fight between the PDN and the PUN - circuit is ratioed so PDN wins, eventually Note Psc during switching period when PDN and keeper are both on simultaneously

Issues in Dynamic Design 2: Charge Sharing EE141 Issues in Dynamic Design 2: Charge Sharing B = Clk X C L a b A Out M p V DD e Charge stored originally on CL is redistributed (shared) over CL and CA Lead to a drop on the output voltage May cause incorrect output (e.g., the next stage is a Inverter gate). CA initially discharged and CL fully charged.

EE141 Charge Sharing B = Clk X C L a b A Out M p V DD e

Example of Charge Sharing (I) Worst case: : Switching voltage of Inverter

Example of Charge Sharing (II)

Solution to Charge Redistribution EE141 Solution to Charge Redistribution Clk Clk Mp Mkp Out A B Clk Me Precharge critical internal nodes using a clock-driven transistor (at the cost of increased area and capacitance) All internal nodes are charged to Vdd during pre-charge  No charge sharing occurs.

Issues in Dynamic Design 3: Backgate Coupling EE141 Issues in Dynamic Design 3: Backgate Coupling Clk Mp Out1 =1 Out2=0 CL1 CL2 In A=0 B=0 Clk Me Due to capacitive backgate coupling between the internal and output node of the static gate and the output of the dynamic gate, Out1 voltage reduces Dynamic NAND2 Static NAND2

Backgate Coupling Effect EE141 Backgate Coupling Effect Voltage Time, ns Clk In Out1 Out2 Clock feedthrough Out1 overshoots Vdd (2.5V) due to clock feedthrough And Out2 never quite makes it to GND Output of static NAND gate does not drop all the way down to GND with the degraded Out1

Issues in Dynamic Design 4: Clock Feedthrough Coupling between Out and Clk input of the precharge device due to the gate-to-drain capacitance. The voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out. May cause Latch-up! Clk Mp Out CL A B Clk Me Danger is that signal levels can rise enough above VDD that the normally reverse-biased junction diodes become forward-biased causing electrons to be injected into the substrate.

Cascading Dynamic Gates EE141 Cascading Dynamic Gates V Clk Clk Clk Mp Mp Out2 Out1 In In Out1 VTn Clk Clk Me Me Out2 V ??? Out2 should remain at VDD since Out1 transitions to 0 during evaluation. However, since there is a finite propagation delay for the input to discharge Out1 to GND, the second output also starts to discharge. The second dynamic inverter turns off (PDN) when Out1 reaches VTn. Setting all inputs of the second gate to 0 during precharge will fix it. Correct operation is guaranteed (ignoring charge redistribution and leakage) as long as the inputs can only make a single 0 -> 1 transition during the evaluation period t Only ONE 0  1 transition allowed at inputs during Evaluation Phase

Domino Logic Combat leakage & Charge sharing! Clk Clk Out1 Out2 In1 EE141 Domino Logic Combat leakage & Charge sharing! Clk Mp Mkp Clk Mp Out1 Out2 1  1 1  0 0  0 0  1 In1 In4 PDN In2 PDN In5 In3 Clk Me Clk Me Ensures all inputs to the Domino gate are set to 0 at the end of the precharge period. Hence, the only possible transition during evaluation is 0 -> 1

Why the Name “Domino”? Like falling dominos! Ini PDN Inj Ini Inj PDN EE141 Why the Name “Domino”? Ini PDN Inj Ini Inj PDN Ini PDN Inj Ini PDN Inj Clk Clk Like falling dominos!

Properties of Domino Logic EE141 Properties of Domino Logic Only non-inverting logic can be implemented! Very high speed tpHL=0. Inverter can be sized to match Fan-out. Input capacitance reduced – smaller logical effort First 32 bit micro (BellMAC 32) was designed in Domino logic Now a rather rare design style due to non-inverting logic only

Restructuring Logic for Domino Circuits Use simple Boolean Transform such as DeMorgan’s Law!

Multiple-output Domino Circuits Function of O3 = (C+D) can be reused!

Compound Domino Logic uses Complex Static Gates at the Output

Designing with Domino Logic EE141 Designing with Domino Logic V DD V DD V DD Clk M Clk M p p M Out1 r Out2 In 1 In PDN In PDN 2 4 In 3 Can be eliminated! Clk M Clk M e e Inputs = 0 during precharge

EE141 Footless Domino The first gate in the chain needs a foot switch Precharge is rippling – short-circuit current A solution is to delay the clock for each stage

Differential (Dual Rail) Domino EE141 Differential (Dual Rail) Domino off on Clk Clk Mp Mkp Mkp Mp Out = AB Out = AB 1 0 1 0 A !A !B B Clk Me AND/NAND differential logic gate. The inputs and their complements come from other differential DR gates and thus all inputs are low during precharge and make a conditional transition from 0 to 1. Annotations show state during evaluate cycle (CLK = 1) Expensive - but can implement any arbitrary function. Use significant power since they have a guaranteed transition every single clock cycle (regardless of signal statistics, since either Out or !Out will transition from 0 to 1). Not ratioed (even though have a cross-coupled PMOS pair) Solves the problem of non-inverting logic

EE141 np-CMOS Clk Me Clk Mp Out1 1  1 1  0 In4 PUN In1 In5 In2 PDN 0  0 0  1 In3 Out2 (to PDN) Clk Mp Clk Me Also called zipper logic - In4 and In5 must be from PDN’s DEC alpha uses np-CMOS logic (Dobberpuhl) Have to size the PUN’s to equalize the delay to that of the PDN’s Really dense layouts and very high speed (20% faster than domino with the correct sizing) Reduced noise margin (as with any dynamic gate) Have two clock signals to generate and route - CLK and !CLK Only 0  1 transitions allowed at inputs of PDN Only 1  0 transitions allowed at inputs of PUN

NORA Logic Clk Clk Out1 In4 PUN In1 In5 In2 PDN In3 Out2 (to PDN) Clk EE141 NORA Logic Clk Me Clk Mp Out1 1  1 1  0 In4 PUN In1 In5 In2 PDN 0  0 0  1 In3 Out2 (to PDN) Clk Mp Clk Me NORA - no race CMOS To other PDN’s To other PUN’s WARNING: Very Sensitive to Noise!

Summary of Dynamic CMOS Dynamic circuits should be designed with care (watch out charge sharing, etc.) It has smaller footprint and higher speed, but may not be best for low-power designs. The current trend is towards an increased use of complementary static CMOS Design Automation Tools: Optimization at the logic level, rather at the circuit level.