Week 5, Verilog & Full Adder Introduction to Digital System and Microprocessor Design Inhwan Lee, Youngtaek Oh, Daehyun Ahn (inhwan301, koyt1126, daehyun.ahn)@postech.ac.kr Mar 20, 2018 1/24

Contents Hardware Design Flow FPGA Verilog: Half Adder Design Exercise: Two Bit Full Adder Design 2/24

Basic Logic Design with Verilog, Kwon Suknam Hardware Design Flow RTL Editor Simulation Logic Synthesis Gate Level Place & Route Post Gate Level Tape Out Designer RTL Code Gate Level Code Physical Layout Chip Verilog Level High Low Cost Basic Logic Design with Verilog, Kwon Suknam 3/24

Area Efficient FPGA Architecture For Datapath Circuits, Omesh Mutukuda A field-programmable gate array (FPGA) an integrated circuit designed to be configured by a customer or a designer after manufacturing Field-Programmable Gate Array, Wikipedia Ref) Field-Programmable Gate Array, Wikipedia Area Efficient FPGA Architecture For Datapath Circuits, Omesh Mutukuda 4/24

FPGA: Pros and Cons (+) Development Efficiency Less time, cost, error correcting for development For testing your Verilog code or need to change design very frequently. (-) Low performance, resource usage, power consumption slow, not for complex system, high power consumption, Large Space … Cost is low for manufacturing (no redundancies) If you want to sell, use ASIC, Application Specific Integrated Circuit, instead) 5/24

Verilog Syntax Hardware Description Language (HDL) Allows for modeling and simulation (with timing) of digital design Can be synthesized into hardware (netlist) by synthesis tools. Two major languages: Verilog, VHDL (Very-high-speed integrated circuits HDL) Verilog: adv. Development Efficiency One of the most popular HDL Less time, cost, error correcting for development For testing your Verilog code or need to change design very frequently. Verilog: dis. Low performance, resource usage, power consumption slow, not for complex system, high power consumption, Large Space … Cost is low for manufacturing (no redundancies) If you want to sell, use ASIC, Application Specific Integrated Circuit, instead) 6/24

Verilog Syntax: Data Types The method for dealing with the digital data in Verilog. There are two basic types: Register/Nets Register => For sequential logic most common type is “reg” the place where data is stored and hold their value before change. Give value in always/initial block. Can be used for latch/flip flops. It does not mean physical register; think it as variable that store value in C. Nets => For combinational logic most common type is “wire” virtual wire that will be physical wire between registers. Not hold value; it just use register’s value. Assign means connect nets with register, gate’s output, or real value. 7/24

Verilog Syntax: Wire Case Register Value of A == value that register hold Wire A Value of D == the gate’s output Wire B Gate Wire D Wire C VDD Value of E == always 1 Wire E GND Value of F == always 0 Wire F 8/24

Verilog: Example (Half Adder) Let’s make Half Adder together step by step.  Please interrupt me when you need any assistance !! Create New Project File – New Project Insert ‘Name’ and ‘Location’ Select Top-level source type ‘HDL’ and then clock ‘Next >’ 9/24

Verilog: Example (Half Adder) Edit the Project Settings following specification (from sheet of the kit) And then click ‘Next’ – ‘Finish’ 10/24

Verilog: Example (Half Adder) Click ‘New Source’ icon to create empty Verilog file. 11/24

Verilog: Example (Half Adder) Select ‘Verilog Module’ to make empty Verilog file. Insert ‘File name’ and choose a proper ‘Location’ Click ‘Next >’ – ‘Next’ – ‘Finish’ 12/24

Verilog: Example (Half Adder) Unit Precision xor Wire c and Wire a Wire b and Assign connects RHS to LHS wire 13/24

Verilog: Example (Half Adder) Run ‘Synthesize’ (Left) You can ‘View RTL Schematic’ (Right) and ‘Check Syntax’ 14/24

Verilog: Example (Half Adder) Let’s simulate the half adder block with ‘testbench’ Click ‘New source’ and select ‘Verilog Test Fixture’ Insert ‘File name’ and click ‘Next >’ 15/24

Verilog: Example (Half Adder) Select Associate Source (where to apply testbench) and then click ‘Next >’ – ‘Finish’ 16/24

Verilog: Example (Half Adder) unit / precision Use ‘reg’ to hold input data ‘initial’ runs when this testbench starts up. #(delay time) 17/24

Verilog: Example (Half Adder) Click ‘Simulate Behavioral Model’ You can confirm simulation result. 18/24

Verilog: Example (Half Adder) Let’s program FPGA. Cheer up, this is the last stage  Run ‘PlanAhead’ to do ‘I/O Pin Planning’ Double-click ‘I/O Pin Planning (PlanAhead) – Pre-Synthesis Click ‘Yes’ – ‘Close’ 19/24

Verilog: Example (Half Adder) Let’s do pin planning referring to FPGA document. (I already uploaded the document on CiTE221 class webpage) 20/24

Verilog: Example (Half Adder) Insert ‘Site’ referring to pin map. File – Save constraints then exit the window Change LED_D(2) site to AF7 21/24

Verilog: Example (Half Adder) Click ‘Implement Design’ and ‘Generate Programming File’ sequently. Double-click ‘Configure Target Device’ and then ‘OK’ 22/24

Verilog: Example (Half Adder) After connect the Kit, double-click the ‘Boundary Scan’. Right click and click ‘Initialize Chain’ Bypass the ‘xcf08p’ and open bit file for ‘xc3s1000’, then program. Test your program using buttons and LEDs on FPGA. 23/24

Two Bit Full Adder Design Let’s make Two Bit Full Adder referring to next One Bit Full Adder Verilog code. Ask us!! We will explain it kindly. 24/24