Status & perspectives of the R&D on DNW MAPS Valerio Re INFN Pavia and University of Bergamo SuperB Workshop Frascati, September 27 – 30, 2010 V. Re SuperB Workshop, Frascati, September 29, 2010

SuperB SVT Layer 0 technology options Striplets option: mature technology, not so robust against background occupancy. Marginal with back. rate > 100 MHz/cm2 Moderate R&D needed on FE chip module interconnection/mechanics Hybrid Pixel option: viable, slightly marginal. Reduction of total material at 1%X0 doable. Reduction of front-end pitch to 50x50 μm2  Produced and tested FE prototype chip with 50x50 μm2 pitch & fast data push readout (already developed for DNW MAPS) - (4k pixels, ST 130 nm) CMOS MAPS option: Sensor & readout in 50 μm thick chip! Extensive R&D (SLIM5-INFN Collaboration) on Deep N-well devices 50x50μm2 with in-pixel sparsification. Fast readout architecture implemented CMOS MAPS (4k pixels) successfully tested with beams. Thin pixels with 3D Vertical Integration: reduction of material and improved performance Two options are being pursued (VIPIX – INFN Collab.) DNW MAPS with 2 tiers Hybrid Pixel: FE chip with 2 tiers + high resistivity sensor Complexity 2D MAPS and 3D pixels are the two most advanced options for a Layer0 upgrade: Sensor Digital tier Analog tier Wafer bonding & electrical interconn. V. Re SuperB Workshop, Frascati, September 29, 2010

Deep N-Well (DNW) sensor concept New approach in CMOS MAPS design compatible with data sparsification architecture to improve the readout speed potential PREAMPL SHAPER DISC LATCH Classical optimum signal processing chain for capacitive detector can be implemented at pixel level: Charge-to-Voltage conversion done by the charge preamplifier The collecting electrode (Deep N-Well) can be extended to obtain higher single pixel collected charge (the gain does NOT depend on the sensor capacitance), reducing charge loss to competitive N-wells where PMOSFETs are located Fill factor = DNW/total n-well area ~90% in the prototype test structures

Status of Deep N-Well MAPS The first generation of Deep N-Well CMOS MAPS with in-pixel sparsification and time stamping was successfully tested. Sensors with different sparsified readout architectures and pixel pitches were developed for SuperB (large background, equivalent to a continuous beam operation) and for ILC (intertrain readout) in INFN programs. SLIM5 APSEL4D SDR0 Average Signal for MIP (MPV) =980e- 90Sr electrons S/N=23 32x128 matrix. Data Driven, continuously operating sparsified readout Beam test Sep. 2008 16x16 matrix, Intertrain sparsified readout 25x25 um pitch Noise events Cluster signal (mV) 50x50 um pitch V. Re SuperB Workshop, Frascati, September 29, 2010

Periphery readout logic ciao APSEL4D In the active sensor area we minimized: logical blocks with PMOS to reduce the area of competitive n-wells digital lines for point to point connections to allow scalability of the architecture with matrix dimensions 32x128 pix - 50 mm pitch perif & spars logic 4K(32x128) 50x50 μm2 matrix subdivided in MacroPixel (MP=4x4) with point to point connection to the periphery readout logic: Register hit MP & store timestamp Enable MP readout Receive, sparsify, format data to output bus S/N ~ 20 with power consumption ~ 30 mW/ch Signal for MIP (MPV) =980e- 90Sr electrons Data lines in common 2 MP private lines MP 4x4 pixels Periphery readout logic Column enable lines in common Data out bus S/N=23 Landau mV Noise events Cluster signal (mV) Threshold dispersion = 60 e- Gain = 860 mV/fC V. Re SuperB Workshop, Frascati, September 29, 2010 saluti

Recent R&D activities on DNW MAPS Radiation tolerance tests with g-rays and neutrons on APSEL devices (2D 130 nm) (see talk by Stefano Bettarini on Monday) Vertically integrated DNW active pixel sensors 65 nm CMOS MAPS V. Re SuperB Workshop, Frascati, September 29, 2010

Radiation Damage Tests with g-rays ciao Radiation Damage Tests with g-rays 60Co g-ray irradiation, 100°C/168h annealing of APSEL3T (3x3, 8x8 devices with analog output) ~10 Mrad maximum integrated dose, 9 rad/s dose rate, MAPS biased as in real application Charge sensitivity GQ decreases with dose; this is mostly due to threshold shifts in the narrow-channel preamplifier and shaper feedback transistors ENC increases with dose; significant recovery after 100ºC/168h annealing ENC degradation after irradiation is mostly due to the increase of low frequency noise in the preamplifier input transistor, because of the noise contribution of the the lateral parasitic transistors associated to the radiation-soft shallow trench isolation oxides V. Re saluti

Radiation Damage Tests with g-rays Charge collection properties are affected by 60Co g-rays to a very little extent (very little bulk damage) V. Re SuperB Workshop, Frascati, September 29, 2010

Testbeam with MAPS exposed to g-rays - 2009 July 2009 CERN Testbeam Results for MAPS (3x3 matrix) with analog output (pre/post irrad. 10 Mrad 60Co  ) Qcluster ~1040 e- for M1 (930 e- for M2) S/N~15-20 depending on the electrode geometry Efficiency~90% for both M1,2 in agreement with the measurements on digital MAPS Modest reduction in collected charge and efficiency in chip irradiated up to 10 Mrad ENC increased by ~35% apsel3T1 M1 - 3x3 cluster signal 120 Gev pions - after 10 Mrad M1 - chip 8 not irradiated M1 chip 24 @ 10 Mrad THR < 4 s Noise Efficiency S = 1003 e- Thr. e- V. Re SuperB Workshop, Frascati, September 29, 2010

DNW MAPS irradiated with neutrons Charge collection decreases when fluence exceeds about 1012 n/cm2 (smaller effect if sensing diode has satellite electrodes; to be continued up to 5 . 1012 n/cm2 ) Bulk damage  very little effect on gain and noise V. Re SuperB Workshop, Frascati, September 29, 2010

MAPS and Vertical Integration Overcome limitations typically associated to “classical” and DNW CMOS MAPS: Reduced pixel pitch 100 % fill factor (few or no PMOS in the sensor layer) Better S/N vs power dissipation performance (smaller sensor capacitance) Reduction of digital-to-analog interferences Increased pixel functionalities (removal of layout constraints allow for an improved readout architecture, analog information,….) Fully-depleted, high-resistivity substrate: larger signal, fast charge collection, radiation hardness, ….. V. Re SuperB Workshop, Frascati, September 29, 2010

The first 3D CMOS MAPS in the APSEL family in the first 3D-IC MPW run ciao The first 3D CMOS MAPS in the APSEL family in the first 3D-IC MPW run Tezzaron/Chartered technology (Fermilab MPW run) NMOS PMOS Digital section Deep N-well sensing electrode Analog section 1st tier P-well N-well P-type epilayer or substrate 2D CMOS technology 2nd tier 3D vertical integration 3DIC Consortium: hosted by Fermi National Accelerator Laboratory, focused on vertical integration, about 15 institutions from U.S., France, Germany, Italy (VIPIX collaboration), Poland, Spain. This Consortium, as a first step, is going to investigate 3D devices based on two layers (“tiers”) of the 130 nm CMOS technology by Chartered Semiconductor, vertically integrated with the Tezzaron interconnection technology. V. Re SuperB Workshop, Frascati, September 29, 2010 saluti

ciao V. Re SuperB Workshop, Frascati, September 29, 2010 saluti

V. Re SuperB Workshop, Frascati, September 29, 2010

The (long) story of the first 3D-IC run MPW run submission in May 2009 During the second half of 2009 and early 2010, the designs were reworked to correct DRC errors, make design changes, implement new design rules, accommodate new requests from the foundry, and correct mask house mistakes (tedious and painful). Frame finally accepted by the mask house in March 2010. Meanwhile, Chartered acquired by GlobalFoundries Currently Tezzaron has about 150 wafers being processed at Chartered for 3D assembly. The 3D-IC Consortium has a lot of 25 wafers with a back up lot of 16 wafers. In July, six of our wafers were at transistor contacts and the remaining 25 wafers had thin oxide transistors completed and thick oxide transistors being fabricated. (DARPA wafers completed and shipped to Ziptronix for 3D assembly using the DBI process) Still waiting for chips: delay appears related to Global/Chartered decision to move some equipment from prototype line, where 3D wafers are done, to the production line due to increased production demands. Generally speaking, due to high production workload the fabrication schedule of CMOS MPW runs in all foundries is currently delayed. V. Re SuperB Workshop, Frascati, September 29, 2010

The second 3D-IC run: technology changes Recent Developments for Future Runs: – Chartered to stop TSVs on 8 inch 130 nm CMOS wafers for the foreseeable future – Chartered agrees to process wafers from FEOL through M4 – Tezzaron will have TSVs added outside the foundry, from M4 down into the substrate and complete the BEOL processing including the bond interface metallization – Implication is that space will need to be left open on M1-M4 for the vias to pass through. – Future potential benefit will be that wafers from other foundries (also with mixed technologies, e.g. 65 nm, SiGe,…) can use the Tezzaron 3D process. - In Europe, the run will be handled by CMP. V. Re SuperB Workshop, Frascati, September 29, 2010

New Tezzaron Process Flow using “Near End of Line” TSV Dielectric(SiO2/SiN) Gate Poly STI (Shallow Trench Isolation) Oxide Silicon W (Tungsten contact & via) Al (M1 – M5) Cu (M6, Top Metal) Dielectric(SiO2/SiN) Gate Poly STI (Shallow Trench Isolation) Oxide Silicon W (Tungsten contact & via) Al (M1 – M5) Cu (M6, Top Metal) 1- Standard CMOS process stopped at MET4 2- Deep etching (DRIE) DBI Dielectric(SiO2/SiN) Gate Poly STI (Shallow Trench Isolation) Oxide Silicon W (Tungsten contact & via) Al (M1 – M5) Cu (M6, Top Metal) Dielectric(SiO2/SiN) Gate Poly STI (Shallow Trench Isolation) Oxide Silicon W (Tungsten contact & via) Al (M1 – M5) Cu (M6, Top Metal) TSV 3- Dielectric isolation and TSV formation 4- Continue BEOL with Via4 / M5 / Via5 / M6 SuperB Workshop, Frascati, September 29, 2010

New Tezzaron Process Flow using “Near End of Line” TSV DBIs continuing the stacking Bond pad for wire bonding or bump, flip-chip … SuperB Workshop, Frascati, September 29, 2010

VIPIX plans and designs The second 3D-IC run: VIPIX plans and designs The VIPIX collaboration is at an advanced stage in the design work for the second MPW run in the 3D Tezzaron/Chartered process. New VIPIX designs will cover an area of about 150 mm^2 of 3D stacked chips (300 mm^2 in terms of planar silicon). Submission deadline will be 1Q2011, to allow enough time for testing devices from the first run. The following devices will be included by VIPIX in the second run, targeting SuperB SVT specifications: “test beam grade” MAPS : 100x128, 50 um pitch (~32 mm2 active area) with high rate sparsified readout architecture a 3D readout chip for high resistivity pixel sensors (similar architecture) : 128x32, 50 um pitch (~10.3 mm2 active area) V. Re SuperB Workshop, Frascati, September 29, 2010

Vertically integrated MAPS in the second 3D-IC run: APSEL Beam axis 1.6 mm 0.5 mm 0.25 mm ~ 38 Pad – pitch 130 mm Piste data line di 2 sottomatrici 0.16 mm 6.4 mm Submatrix 1: 128x50 128x100 pixel matrix 50 mm pitch Active area=32mm2 Readout=8mm2 Area~x2x area from FE32x128 5 mm 5.56 mm ~ 38 Pad – pitch 130 mm ~ 38 Pad – pitch 130 mm Submatrix 2: 128x50 Piste data line di 2 sottomatrici 0.16 mm 0.120 mm cut line 8.99 mm V. Re SuperB Workshop, Frascati, September 29, 2010

An example of how 3D integration is exploited in the second run: in-pixel logic with time-stamp latch for a time-ordered readout No Macropixel Timestamp (TS) is broadcast to pixels & pixel latches the current TS when is fired. Matrix readout is timestamp ordered A readout TS enters the pixel, and a HIT-OR-OUT is generated for columns with hits associated to that TS. A column is read only if HIT-OR-OUT=1 DATA-OUT (1 bit) is generated for pixels in the active column with hits associated to that TS TSComp. DATA-OUT HIT-OR-OUT This more complex in pixel logic will be implemented with 3D integration without reducing the pixel collection efficiency even improving the readout performance (readout could be data push or triggered) VHDL simulation of the data push chip (100MHz/cm2 input hit rate) Readout Effi > 99 % @ 50 MHz clock with timestamp of 200 ns. V. Re

High resistivity pixels Pixel sensors on high resistivity substrate (compared to MAPS) give much better radiation hardness, signal-to-noise ratio,… Sensors are fabricated by FBK-IRST, following the specifications of the interconnection process A prototype pixel sensor matrix is ready and characterized N-on-N: P-spray isolation on n-side, p implant on the back side Wafer thickness: 200 mm (FZ, HR Si); 50x50 mm pitch. Two alternatives for the interconnection process: Bump bonding with the IZM Berlin process First test of the process with 2D 130 nm chip prototypes under way Vertical integration with T-Micro/Zycube (Japan): might offer lower cost and more flexibility with respect to Ziptronix V. Re SuperB Workshop, Frascati, September 29, 2010

65 nm APSEL The demand for higher in-pixel functionalities along with the reduction of pixel cell size drives the interest of the designers community towards sub-100 nm CMOS processes in the design of mixed signal front-end electronics We studied the properties of Low-Power 65 nm CMOS where the supply voltage (1.2 V) does not scale with respect to 130 nm CMOS and the gate leakage current is very low Noise parameters appear stable with respect to previous CMOS generations The comparison with data from previous CMOS generations confirms the high degree of tolerance to ionizing radiation typical of sub-100 nm technologies We designed a prototype chip with mixed-signal readout circuits in a 65 nm CMOS process by IBM (10LPE/10RFE)  APSEL65 V. Re SuperB Workshop, Frascati, September 29, 2010

APSEL65 DNW MAPS Classical signal processing chain for capacitive detector The analog processor includes a charge sensitive amplifier, a shaping stage and a threshold discriminator  binary readout V. Re SuperB Workshop, Frascati, September 29, 2010

Features & Post layout simulation results W/L PA input device: 27/0.25 Power consumption: 20 μW Equivalent noise charge: 38 e- Threshold dispersion: 38 e- (main contributions from shaper input device and NMOS and PMOS pair in the discriminator) Charge sensitivity: 725 mV/fC Peaking time: 300 ns SuperB Workshop, Frascati, September 29, 2010

Cell layout In this prototype the digital section is kept to a minimum (latch, OR gate, tri- state buffer). It is planned to include sparsification and time- stamping logic at the pixel level in more advanced versions (room for this already available) 40 um n-well PMOSFETs (area ≈ 50 µm2) Sensor (area ≈ 360 µm2) SuperB Workshop, Frascati, September 29, 2010

Digital output of the central pixel Test chip layout 8x8 DNW MAPS matrix - digital outputs - outputs of the shapers can be accessed through row and column decoders and read out one at time 3 fast-channels with Cinj and detector simulating capacitor (50 fF, 100 fF, 150 fF) 3 standalone channel with Cinj and detector simulating capacitor (250 fF, 350 fF, 450 fF) 3x3 DNW MAPS matrix 9 analog outputs Digital output of the central pixel Cinj on central pixel SuperB Workshop, Frascati, September 29, 2010

SuperB Workshop, Frascati, September 29, 2010 Conclusions Advanced microelectronic technologies (3D, sub-100 nm CMOS) provide exciting opportunities for high performance MAPS and fully depleted pixel sensors A lot of work is needed to qualify these technologies for actual experiments Second run with 3D Tezzaron/Chartered technology and large MAPS matrix and pixel readout chip foreseen in early 2011 V. Re SuperB Workshop, Frascati, September 29, 2010

Backup slides V. Re

Via First Approach Through silicon Via formation is done either before or after CMOS devices (Front End of Line) processing Form vias before transistors IBM, NEC, Elpida, OKI, Tohoku, DALSA…. Tezzaron, Ziptronix Chartered, TSMC, RPI, IMEC…….. Form transistors before vias TWEPP-08

Via Last Approach Via last approach occurs after wafer fabrication and either before or after wafer bonding Zycube, IZM, Infineon, ASET… Samsung, IBM, MIT LL, RTI, RPI…. Notes: Vias take space away from all metal layers. The assembly process is streamlined if you don’t use a carrier wafer. TWEPP-08

Bonding Choices Electrical and Mechanical Bonds Fermilab experience (MIT LL) (RTI) (Tezzaron) (Ziptronix) TWEPP-08