CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 15 March 9 W’05 Yutao He yutao@cs.ucla.edu 4532B Boelter Hall http://courseweb.seas.ucla.edu/classView.php?term=05W&srs=187154200

Outline Recap - Combinational macro modules Decoders Encoders Shifters Combinational macro modules Multiplexers Demultiplexers Chapter 11 Sequential Modules Registers Shift registers

Chapter 9 - Overview Basic Questions: Combinational Systems Gate networks (AND, OR, NAND, etc.) Chapters 2-6 Design Analysis Module networks (DEC/ENC, MUX/DEMUX, Shifter.) Chapter 9 Basic Questions: What are each module’s property? inputs, outputs, functions (high-level and binary level) How to implement it using logic gates? How to design a comb. system using these modules? How to analyze a comb. system using these modules?

Multiplexer (MUX) EN E Multiplexer 2n-Input 1 2n-1 x0 x1 x2n-1 1 2n-1 x0 x1 x2n-1 Data Inputs z Data Output n-1 sn-1 s0 Selection Inputs

Multiplexer - Specification High-Level Binary-Level

Implementation of MUX with AND/OR gates Multiplexer - Implementation (1) Implementation of MUX with AND/OR gates

Implementation of MUX with transmission gates Multiplexer - Implementation (2) Implementation of MUX with transmission gates

Multiplexer (Tree) Networks s3 s2 s1 s0 = 1001 1 1 z = x9

Applications of MUXes n-bit Simple Shifter

Applications of MUXes (Cont’d) 4-bit Right-3 Unidirectional Shifter

Design Using MUXes Key observations: Basic Idea: A 2n-Input MUX corresponds to a n-input switching function. Data outputs store output values of the switching function. Selection inputs correspond to the inputs of the switching function. A 2n-Input MUX stores the truth table of a n-input switching function. Basic Idea: MUXes are Universal Set assuming constants 0 and 1 are available EN E Multiplexer 2n-Input 1 2n-1 x0 x1 x2n-1 n-1 sn-1 s0 z

Example 9.12 - One-Bit Full Adder y carry_in sum carry-out x 1 y Cin S Cout Need two 8-Input MUXes

One-Bit Full Adder (Cont’d) EN Multiplexer 8-Input 1 2 x Cin s y 3 4 5 6 7 Cout x 1 y Cin S Cout 1 1

Design Using MUXes with Small Sizes Is it possible to design a n-input switching function using a 2m-input MUX, where m < n? The answer is Yes! How? Basic idea: Use data inputs of a MUX to store variables Basic approaches: Truth table K-Map Boolean algebra

1-Bit FA Revisited: Using Truth Table Uses 4-input Muxes EN E = 1 4-Input MUX 1 s 2 3 x 1 y Cin S Cin Cin C’in C’in C’in Cin x y

Using Truth Table (Cont’d) EN E = 1 4-Input MUX 1 x Cout y 2 3 x 1 y Cin Cout Cin 1 Cin Cin 1

1-Bit FA Revisited: Using K-Map 0 1 3 2 4 5 7 6 x Cin y 0 1 1 0 x y Cin C’in C’in Cin Cin C’in EN E = 1 4-Input MUX 1 x s y 2 3

Using K-Map (Cont’d) Cin Cin 1 x y 0 0 0 1 1 0 1 1 x y 0 Cin Cin 1 EN 0 1 3 2 4 5 7 6 x Cin y 0 0 0 1 1 0 1 1 x y 0 Cin Cin 1 Cin 1 EN E = 1 4-Input MUX x Cout y 2 3

1-Bit FA: Using Boolean Algebra S = x’y’Cin + x’yC’in + xy’C’in + xyCin = (x’y’)Cin + (x’y)C’in + (xy’)C’in + (xy)Cin m0 m1 m2 m3 Cin C’in EN E = 1 4-Input MUX 1 x s y 2 3

Using Boolean Algebra (Cont’d) Cout = x’yCin + xy’Cin + xyC’in + xyCin = (x’y)Cin + (xy’)Cin + (xy)(C’in + Cin) = (x’y)Cin + (xy’)Cin + (xy) m1 m2 m3 Cin 1 EN E = 1 4-Input MUX x Cout y 2 3

Design Using Network of 2-Input MUXes z = x0s’+x1s EN E 2-Input MUX 1 s z x0 x1 EN E = 1 2-Input MUX 1 x z EN E = 1 2-Input MUX 1 x0 z x1 NOT gate z = x’ AND gate z = x0 x1

Shannon Theorem The Formula: The idea: The Application: f(xn-1, …, x1, x0) = f(xn-1, …, x1, 0) x’0+ f(xn-1, …, x1, 1) x0 The idea: A function with more inputs can be decomposed into two functions with fewer inputs. The Application: A n-input switching function can be implemented with 2-input MUXes by repeatedly applying the Shannon Theorem. EN E 2-Input MUX 1 x0 f(xn-1, …, x1, x0) f(xn-1, …, x1, 0) f(xn-1, …, x1, 1)

Example 6.8 Implement the following function with 2-Input MUXes: f(x3, x2, x1, x0) = x3( x1+ x2x0) Decomposition: The first level: f(x3, x2, x1, 0 ) = x3 x1 f(x3, x2, x1, 1 ) = x3 ( x1 + x2) The second level: f(x3, x2, 0, 0 ) = 0 f(x3, x2, 0, 1 ) = x3x2 f(x3, x2, 1, 0 ) = x3 f(x3, x2, 1, 1 ) = x3

Example 6.8 (Cont’d) The third level: x3 x3 f(x3, 0, 0, 0 ) = 0, f(x3, 1, 0, 0 ) = 0 f(x3, 0, 0, 1 ) = 0, f(x3, 1, 0, 1 ) = x3 f(x3, 0, 1, 0 ) = x3, f(x3, 1, 1, 0 ) = x3 f(x3, 0, 1, 1 ) = x3, f(x3, 1, 1, 1 ) = x3 f 1 x1 x0 x2 x3 f 1 x1 x0 x2 x3

Demultiplexer (DEMUX) EN E y0 1 y1 Data Inputs Demultiplexer 2n - Output Data Output x 2n-1 y2n-1 n-1 sn-1 s0 Selection Inputs

Demultiplexer: High-Level Spec

Example 9.13: 4-Output DEMUX

4-Output DEMUX (Cont’d)

Application of DEMUXes

Chapter 11 Sequential Modules Sequential Systems Flip-Flops (D, JK, SR, T FFs, etc.) Chapters 7-8 Design Analysis Module networks (Register, Shift Register, Counter) Chapter 11 Basic Questions: What are each module’s property? inputs, outputs, functions (high-level and binary level) How to implement it using FFs and logic gates? How to design a sequential system using these modules? How to analyze a sequential system using these modules?

n-Bit Register

n-Bit Register - High-Level Spec

4-Bit Register - Implementation

Timing Behavior of Registers

Design Using Registers Example 11.1

Example 11.1 - Using FFs

Example 11.1- Using Register LD 2-Bit Register CLK CLR y0 y1 Y1 Y0 When x = 1

Shift Registers Basic Types: Serial In/Serial Out (SI/SO): m=n=1 CLK Shift Register CTL n Basic Types: Serial In/Serial Out (SI/SO): m=n=1 Serial In/Parallel Out (SI/PO): m=1, n> 1 Parallel In/Serial Out (PI/SO): m>1, n=1 Parallel In/Parallel Out (PI/PO): m, n > 1

Serial-In/Serial-Out Shift Registers

Serial-In/Parallel-Out Shift Registers

Parallel-In/Serial-Out Shift Registers

Parallel-In/Parallel-Out Shift Registers

PI/PO Shift Registers: High-Level Spec

PI/PO Shift Register Control Present state s(t) = 0101, data input x(t)=1110

PI/PO Shift Register: Implementation

Applications of Shift Registers Serial interconnection of two systems

Applications of Shift Registers (Cont’d) Bit-serial operations

Design Using Shift Registers For finite-memory sequential systems, shift registers can be used as the state register: Example 11.2: z(t) = 1 whenever x(t) • x(t-8) = 1

Design Using Shift Registers (Cont’d) Shift registers are handy for implementing pattern detectors Example 11.3 Design a pattern detector that detects 011101101

Networks of Shift Registers

Summary Combinational macro modules Sequential macro modules: MUXes DEMUXes Sequential macro modules: Registers Shift Registers

Next Lecture Chapter 11 Counters Chapter 12 ROM