Unified Model Generation for FPGA-based LHCb VeLo Algorithms

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Presentation transcript:

Unified Model Generation for FPGA-based LHCb VeLo Algorithms Presented by: Manfred Muecke (CERN) Presented at: 12th Workshop on Electronics for LHC and Future Experiments (LECC'06) 25-29 September 2006, Valencia SPAIN VELO overview FPGA-based Algorithms Si strip detector Read-out electronics Baseline VELO design - 21 stations. Each station measures r and  - Left-Right staggered in Z to allow for a small overlap region (alignment) Silicon sensor: n+ in n-bulk sensors Second metal layer for signal routing 2048 micro strips per sensor (Over 170 000 channels in total) 35 – 100 μm pitch (To keep occupancy reasonable at low r) Unified Model Generation (* BwAdapt shows automatic port adaption using Confluence Compiler 0.9.0 pre-release *) with cCalculate Bw A B C1 C2 is component cCalculate +a +b -C1 -C2 C1 <- A '*' B (*unsigned mult+Bit adaption *) C2 <- ('0' '++' A) '+' ('0' '++' B) (* add *) end Bw <- 10 A <- {input "A" 1 Bw $} B <- {input "B" 2 Bw $} C1 <- {output "C1" 1 $} C2 <- {output "C2" 2 $} {cCalculate A B C1 C2} (* compile options*) {set "FileName" "BwAdapt"} {set "BuildName" "BwAdapt"} (* VHDL Top Entity*) {set "GenVhdl" true} {set "GenC" true} Confluence Compiler + Code Generator .cf Common Confluence code base Problem: Two algorithm representations: C for simulation - easy to change - good to explore new algorithms - difficult to keep bit-accurate VHDL for HW implementation - more difficult to change - hardware constraints - resource – accuracy tradeoff Both representations give valuable feedback, but it is very laborious and error-prone to keep them (manually) synchronized. Solutions: C -> VHDL (High-Level Synthesis): Little control over results VHDL -> C (Simulation extraction): more VHDL coding ? -> C + VHDL: if feasible language available Chosen Language: Confluence HDL - Open Source - Functional - Synchronous RTL - First order functions - Type inference - Implicit Synchronization -> Automatic C/VHDL code generation from one common Confluence (RTL) description. Challenges: C++/Vetra Interface Automatic Memory generation Follow Language development Adapt to functional programming paradigm More communication between HW- and simulation-designers original code Cf DSP.cf .fnf FNF FPGA Design (VHDL) DSP (VHDL) System Simulation Framework VETRA (C++) DSP (C) .vhd .v .c CoSimulation Use Cases: improved code DSP.cf First data from ACDC2 processed with Vetra: