32-bitni mikrokontroleri i primena - MS1BMP 2017/2018 Nenad Jovičić Marija Janković

USART SMT32L467RG ima 5 USART-a i jedan LowPowerUART Posebne karakteristike u odnosu na standardni USART: 8 ili 16 bita oversampling Frakcioni baud-rate generator (slično kao MSP) 7, 8 ili 9 bita podatak Encoder decoder za podršku IRDA prenosu Podržan smartcard protocol ISO7816-3 Half-duplex komunikacija preko jedne žice Dva odvojena DMA kanala za predaju i prijem Četrnaest izvora prekida (regularni i oni za detekciju greške) RTS/CTS hardverski handshaking Well, there are differences – important ones. The first difference between a USART and a UART is the way in which the serial data may be clocked. A UART generates its data clock internally to the microcontroller and synchronizes that clock with the data stream by using the start bit transition. There is no incoming clock signal that is associated with the data, so in order to properly receive the data stream the receiver needs to know ahead of time what the baud rate should be. A USART, on the other hand, can be set up to run in synchronous mode. In this mode the sending peripheral will generate a clock that the receiving peripheral can recover from the data stream without knowing the baud rate ahead of time. Alternatively, the link will use a completely separate line to carry the clock signal. The use of the external clock allows the data rate of the USART to be much higher than that of a standard UART, reaching up to rates of 4 Mbps. The second major difference between a USART and a UART is the number of protocols the peripheral can support. A UART is simple and only offers a few options from its base format, such as number of stop bits and even or odd parity. A USART is more complex and can generate data in a form corresponding to many different standard protocols such as IrDA, LIN, Smart Card, Driver Enable for RS-485 interfaces, and Modbus, to name a few. A USART also has the same asynchronous capabilities as a UART, that is, a USART can generate the same type of serial data as seen in Figure 1. RTS/CTS (request to send/ clear to send) – hardware flow control – hardware handshake - The RTS and CTS signals were originally defined for use with half-duplex (one direction at a time) modems Infraref Data – IrDA LIN (Local Interconnect Network) is a serial network protocol used for communication between components in vehicles. The need for a cheap serial network arose as the technologies and the facilities implemented in the car grew, while the CAN bus was too expensive to implement for every component in the car. LIN is a broadcast serial network comprising 16 nodes (one master and typically up to 15 slaves). All messages are initiated by the master with at most one slave replying to a given message identifier. The master node can also act as a slave by replying to its own messages. Because all communications are initiated by the master it is not necessary to implement a collision detection. IrDA – Infrared data association Oversampling – koliko puta može da se sempluje svaki bit prenosa. The following pins are required in RS232 Hardware flow control mode: • RTS: Request to send is receivers signal that is sent to transmitter on line CTS • CTS: Clear to send The TX pin, PA9 should be set up as a push-pull output using the alternate function at low frequency (0b1010). RX is a floating input (0b0100) which is its default state although you may wish to enable the pullup/down feature if it suits your application. 

USART blok šema A common issue with micro controllers is that the baud rate generator is a simple division of the main processor clock. That leads to ‘strange’ system clock frequencies like 4.9152MHz just to get easy divisors for the baud rate generator. The STM32 has a fractional generator that means that pretty well any baud rate can be derived from the system clock whatever its value. Each USART has a register, USART_BRR, that holds the divisor, stored as a 12.4 unsigned fixed point number. The reference manual is a bit awkward on the matter of what value to store in here but the simple answer is to calculate it from USART_BRR = Fck/BAUDRATE This will get you close enough although you should probably use a rounding factor and do it properly.

Multiprocesorska komunikacija Idle line protokol ili korišćenje markera adrese. USART prijemnik može da bude u aktivnom i MUTE modu. U MUTE modu ne generiše prekide i ne postavlja statusne bite. U slučaju korišćenja markera adrese, deo CR2 registra je 4-bitna adresa koja se automatski poredi sa adresom primljenom preko serijske veze.

STM CUBE UART Projekti Predajna ploča pošalje poruku prijemnoj, a nakon toga Prijemna ploča vrati tu istu poruku predajnoj.

STM CUBE Projekat UART_TwoBoards_ComPolling interesantno UserButtonStatus koji treba da pokrene glavni program je tipa __IO koji je volatile da ga optimizacija kompajlera ne bi hardkodovala.

Predajna strana Prevodjenje u zavisnosti da li je ploča predajnik ili prijemnik Sve se implementira preko takozvanih blokirajućih funkcija

Prijemna strana Prijemnik koristi iste funkcije za prijem i kasniju predaju poruke Na kraju se vrši provera poslate i primljene poruke. Ovo ima smisla samo kod predajnika...

How to use this driver? (uvek u stm32l4xx_HAL_PPP.c)

How to use this driver? (uvek u stm32l4xx_HAL_PPP.c)

Svi parametri USART-a Inicijalizacija USART-a Baud rate (frakcioni generator, ako se radi sa 8 bita oversampling-a, 12bita celobrojni deo, 4 bita frakcioni) Word length (7, 8, 9 bita) Stop bits (0.5, 1, 1.5, 2) Parity (none, even, odd) Mode (RX, TX, RX&TX) Hardware flow control (CTS i/ili RTS aktivni ili ne) Oversampling (16 ili 8 bita) One bit sampling (odlucuje se na osnovu jednog semplovanog bita ili na osnovu 3)

Inicijalizacija interesantno UserButtonStatus koji treba da pokrene glavni program je tipa __IO koji je volatile da ga optimizacija kompajlera ne bi hardkodovala.

Pokretanje USART-a HAL_UART_DeInit(&UartHandle) uart state BUSY uart disable clear all control registers uart state RESET HAL_UART_Init(&UartHandle) HAL_UART_MspInit UART_SetConfig __HAL_UART_ENABLE

Svaka posebna periferija, koja pripada nekoj generičkoj klasi, poseduje neke specifičnosti koje se mogu razlikovati kod svakog pojedinačnog mikrokontrolera. Na primer koji pinovi se koriste. To verovatno NIKADA neće ući u sklop generičkih drajvera...

Sve metode poliranja se zasnivaju na čekanju na neki flag Sve metode poliranja se zasnivaju na čekanju na neki flag. U ovom slučaju flag TXE da je predajni buffer spreman za novi podatak. Da bi funkcionalnost bila bar u nekoj meri neblokirajuća uvek se uvodi Timeout.

Timeout funkcionalnost se implementira preko sistemskog tajmera U pitanju je prosta kalkulacija korišćenjem relativnog sistemskog vremena Ako nešto nije u redu preduzimaju se akcije...

HAL drajveri često koriste poling logiku za implementaciju raznih funkcionalnosti i sada je jasno zašto je u okviru HAL_Init() funkcije i inicijalizacija sistemskog tajmera...

STM CUBE Projekat UART_TwoBoards_ComIT Struktura programa je praktično identična, sa razlikom da se funkcije zovu malo drugačije....

STM CUBE Projekat UART_TwoBoards_ComIT Ali, ne postoji TIMEOUT.

USARTx_IRQHandler

HAL_UART_IRQHandler

HAL_UART_IRQHandler

I naravno Callback funkcije Globalna promenljiva koju menjamo samo u prekidnoj rutini, a ispitujemo status u glavnom programu.

A da me vidi optimizer?

Volatile - demistifikacija Volatile se koristi za: Memory-mapped peripheral registers Global variables modified by an interrupt service routine Global variables accessed by multiple tasks within a multi-threaded application

Volatile - primer Primer: Na adresi 0x1234 se nalazi periferijski registar, na primer ulazni osmobitni port. Potrebno če čekati logičku jedinicu na bilo kom ulazu: Kompajler koji štedi prostor će verovatno ovo da prevede na sledeći način:

Ako se koristi Volatile... Daklaracija promenljive: Kako je to kompajler preveo:

U našem slučaju.... Pogrešno bi bilo pretpostaviti da je promenljiva UartReady neki periferijski registar jer nas deklaracija __IO ITStatus UartReady navodi na to. Verovatno bi bilo korektnije napisati jednostavno volatile ITStatus UartReady, ali efekat je isti.

Pitanje Ako definišemo promenljivu volatile uint64_t var Glavni čeka da varijabla postane jednaka nuli var=-10; while(var!=0); Function(); A prekid tajmera radi sledeću stvar: var++; Da li će se funkcija Foo() garantovano izvršiti nakon 10 tajmerskih prekida? Ili možda 11...Ili...?

Zadatak Povezati dve ploče da komuniciraju međusobno pomoću projekta UART_TwoBoards_ComIT Jedna ploča je TRANSMITTER Druga je RECEIVER Na transmiter ploči se pritiskom na USER_BUTTON startuje komunikacija

Zadatak Izmeniti projekat tako da se komunikacija vrši preko UART3 modula Izmeniti projekat tako da se komunikacija vrši preko UART2 modula Datasheet za AF podešavanje pinova

UART 2 ne radi User manual – soldering bridges za PA2 PA3 pinove To je zapravo naš ST-link konektor!

DMA na stm32l476RG Mikrokontroler ima 2 DMA kontrolera (DMA1, DMA2) DMA pruža: 14 nezavisnih kanala preko kojih se primaju DMA zahtevi Svaki kanal proizvodi hardverski DMA zahtev, ali je omogućen i softverski triger na svakom od kanala. Prioriteti zahteva od različitih kanala se softverski mogu podesiti na jedan od 4 dostupna nivoa. Ukoliko stignu zahtevi sa dva kanala istih prioriteta, prelazi se na hardverski prioritet gde kanal manjeg indeksa ima prednost. Podržan prenos 8, 16 i 32-bitnih podataka. Podržani cirkularni baferi Mogući su prenosi u svim kombinacijama između memorije i periferija. Pristup Flash, SRAM memoriji i APB i AHB periferijama kao mogućim izvorima i destinacijama Podržan prenos za tajmere, ADC, SPI, I2Cs, USART i DAC

DMA arhitektura Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 80 MHz. The bus matrix implements round-robin scheduling, thus ensuring at least half of the system bus bandwidth (both to memory and peripheral) for the CPU.

Preklapanje DMA i CPU DMA se preklapa sa CPU-om tako da nikada ne dolazi do potpunog blokiranja jednog ili drugog. The bus matrix implements round-robin scheduling, thus ensuring at least half of the system bus bandwidth (both to memory and peripheral) for the CPU.

DMA prenos Prenos se sastoji iz 4 faze In summary, each DMA transfer consists of three operations: • The loading of data from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register. • The storage of the data loaded to the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register. • The post-decrementing of the DMA_CNDTRx register, which contains the number of transactions that have still to be performed.

DMA1 kanali Reference manual Arbiter The arbiter manages the channel requests based on their priority and launches the peripheral/memory access sequences. The priorities are managed in two stages: • Software: each channel priority can be configured in the DMA_CCRx register. There are four levels: – Very high priority – High priority – Medium priority – Low priority • Hardware: if 2 requests have the same software priority level, the channel with the lowest number will get priority versus the channel with the highest number. For example, channel 2 gets priority over channel 4.

DMA2 kanali - veza sa periferijama

DMA prekidi Svaki DMA kanal ima tri prekida: Transfer završen Transfer na pola Greška u transferu fe

Circular mode Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). When circular mode is activated, the number of data to be transferred is automatically reloaded with the initial value programmed during the channel configuration phase, and the DMA requests continue to be served.

Disable vs DeInit If a DMA channel is disabled, the DMA registers are not reset. The DMA channel registers retain the initial values programmed during the channel configuration phase.

STM CUBE Projekat UART_TwoBoards_ComDMA Struktura programa je praktično identična, sa razlikom da se funkcije zovu malo drugačije....

STM CUBE Projekat UART_TwoBoards_ComDMA Ali, ne postoji TIMEOUT.

Inicijalizacija + Msp init

Msp init – DMA init

Msp init – DMA init

Msp init – DMA init

Msp init – DMA init

STM CUBE Projekat UART_TwoBoards_ComDMA

STM CUBE Projekat UART_TwoBoards_ComDMA

Sumiranje Inicijalizacija UART-a UART_ReceiveDMA Inicijalizacija UART pinova Inicijalizacija pridružene DMA (po jedna za RX i TX) Uvezivanje pokazivača DMA-UART Dozvola prekida i UART-u i DMA kanalima preko kojih su vezani RX i TX UART_ReceiveDMA Sad treba startovati i UART i DMA Prvo se startuje DMA, podese se za RX DMA callback funkcije i startuje se DMA sa dozvoljenim prekidima Startuje se UART periferija

Šta se posle dešava? DMA čeka da se pojavi podatak u RX data registru Kada se pojavi prebacuje ga u memoriju Do kada se ovo ponavlja?

Kada je kraj transfera? Pri pozivu funkcije za transmit i receive korisnik definiše koje je veličine poruka. DMA na onovu te informacije zna kada će se pojaviti prekidi HalfTransfer complete, Transfer complete. Šta se dešava kada se pojavi prekid za kraj transfera?

DMA IRQ handler

DMA IRQ handler

DMA završio, UART stupa na scenu

Zadatak Prošli smo kroz UART_Receive_DMA, prođite sami kroz UART_Transmit_DMA Šta se dešava kada DMA javi da je prosledila sve podatke? Da li smemo da odemo u prekidnu rutinu završenog transfera samo na osnovu završenog DMA transfera?

I2C 3x I2C 1Mbit/s Slave and master modes Multimaster capability Standard-mode (up to 100 kHz) Fast-mode (up to 400 kHz) Fast-mode Plus (up to 1 MHz) 7-bit and 10-bit addressing General call Programmable setup and hold Software reset 1-byte buffer with DMA capability Programmable analog and digital noise filters

SPI 3x SPI QUAD SPI Master or slave operation Full-duplex synchronous transfers on three lines Half-duplex synchronous transfer on two lines (with bidirectional data line) Simplex synchronous transfers on two lines (with unidirectional data line) 4-bit to 16-bit data size selection Multimaster mode capability Slave mode frequency up to fPCLK/2. Programmable clock polarity and phase Programmable data order with MSB-first or LSB-first shifting Dedicated transmission and reception flags with interrupt capability SPI bus busy status flag SPI Motorola support Hardware CRC feature for reliable communication QUAD SPI

QUAD SPI