ERL BPM System Mike Billing, Mark Palmer (J. Dobbins, C. Strohman, E. Tanke) Outline: Overview Parameters Stripline Design and Status Readout Plan Readout Hardware Overview Performance Interface Diagnostic Capabilities Implementation Plan

Overview Requirements: Hardware Need to know all operating configurations for which BPM measurements needed Bunch structure Full possible current range Required position resolution How many bunches to average over Etc Need to specify timing system interface Hardware Will describe progress on stripline development Will give an overview of readout electronics Front Ends Timing Digital Processing DAQ 11/22/2018 ERL BPM System

Parameters Bunch Charge Bunch Length Bunch Spacing BPM Orientation ~8 pC to 80 pC Bunch Length 0.6 -1 mm Bunch Spacing 25 ns 40 MHz Laser Rep Rate 0.77 ns 1.3 GHz Rep Rate 2.3 ns 1.3 GHz/3 Rep Rate Future Interleaved Accelerating & Decelerating Bunches BPM Orientation In plane? 45 degree? Beampipes Striplines for 3.0” OD pipe Other??? BPM Count (and when) Room 128: 4 (early Fall) Phase Ia: ??? Beyond… Resolution Requirements ??? mm Readout Requirements Position Current? Phase? Averaging vs Bunch-by-Bunch Etcetera 11/22/2018 ERL BPM System

Stripline Design & Status Feedthrough Testing Kyocera, MPF, Ceramaseal Ceramaseal checked out for 50W with r < 0.2% while others were ~3-6% Need to place order Stripline Pipe 2.37” ID 3.0” OD Striplines Nominal 30 degree l/4 length 50 W ~1% reflection coefficient Tapered section for impedance matching All tests done without welding 20 mr / div & 0.1 ft/div 11/22/2018 ERL BPM System

Readout Plan 11/22/2018 ERL BPM System

Readout Hardware Overview Use existing BPM module 8-channel BPM Allows for IQ measurement Phase-locked loops CESR 24 MHz 72 MHz ERL 40 MHz 80 MHz Jumper controlled TigerSHARC DSP Ethernet - 100MBit Coldfire chip RTEMs EPICs IOC 11/22/2018 ERL BPM System

Performance Signal Characteristics Noise and Resolution Bunch – use 80 pC Ipeak ~ 10 Amps Tbunch = 0.77 ns Stripline fstrip ~ 0.5 rad Vpeak ~ 20 V x or y ~ 15 mm (D/S) Resonant Circuit Filter Q ~ 20 Center Frequency ~ 1.3 GHz BW ~ 65 MHz Peak Signal Ratio ~ 0.07 Digital Sampling Tavg = 1 ms Navg = 80 (digital averages) Nbunch = 1300 bunches (in 80 avg’s) Noise and Resolution Noise dominated by digital sampling. Fractional errors: sfrac ~ 10-3 (single sample) savg ~ 10-4 Position Resolution sposition ~ 1-2 mm 11/22/2018 ERL BPM System

Interface Communications/Control DAQ Software Present status ERL Plan Control thru XBus interface (MPM access) Ready to test ethernet interface for data transfers ERL Plan All operations via Ethernet Several questions: EPICs IOC in each module? Intermediate level IOC? What level of data processing desired in DSP? DAQ Software Low-level code based on transfers of data packets which are mapped into C structures Replace MPM packet transfers with suitable EPICs packet transfer routines Preserve rest of the existing DAQ (C code) 11/22/2018 ERL BPM System

Diagnostic Capabilities Required Measurement Modes Quad/RF Cavity Reference Centering Stability Mechanical Electronic Optics Correction Beta or phase Coupling Dispersion in arcs Measurement type DC or transient? Pulsed or CW? Trajectory correction and feedback Current Monitoring Fast Feedback Input Timing System Integration/Requirements 11/22/2018 ERL BPM System

Implementation Plan Immediate plans Short-term plans Room 128 BPMs Stripline Prototype Cut final test strip (#3) Weld unit Bench test Electronics Order parts for 6 BPM readout modules Finish Engineering Design Vacuum connections Address trapped volumes Finalize specifications Short-term plans Order all parts Construct first full BPM Prep 1st ERL readout module Prepare beampipe modifications for installation at end of CESR Linac Install during June shutdown Beam test shortly thereafter Use 72 MHz timing Room 128 BPMs Incorporate final modifications by July Produce striplines by early Fall Assemble and test first 4 readout modules by early Fall Finalize DAQ software by early Fall 11/22/2018 ERL BPM System