Introduction to Code Generation

Slides:



Advertisements
Similar presentations
P3 / 2004 Register Allocation. Kostis Sagonas 2 Spring 2004 Outline What is register allocation Webs Interference Graphs Graph coloring Spilling Live-Range.
Advertisements

Architecture-dependent optimizations Functional units, delay slots and dependency analysis.
The Last Lecture Copyright 2011, Keith D. Cooper & Linda Torczon, all rights reserved. Students enrolled in Comp 512 at Rice University have explicit permission.
Introduction to Code Optimization Comp 412 Copyright 2010, Keith D. Cooper & Linda Torczon, all rights reserved. Students enrolled in Comp 412 at Rice.
Introduction to Code Generation Comp 412 Copyright 2010, Keith D. Cooper & Linda Torczon, all rights reserved. Students enrolled in Comp 412 at Rice University.
Intermediate Representations Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp 412 at Rice University.
Code Shape III Booleans, Relationals, & Control flow Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled.
1 Handling nested procedures Method 1 : static (access) links –Reference to the frame of the lexically enclosing procedure –Static chains of such links.
Code Shape II Expressions & Arrays Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved.
Improving code generation. Better code generation requires greater context Over expressions: optimal ordering of subtrees Over basic blocks: Common subexpression.
Instruction Selection Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved.
The Procedure Abstraction Part I: Basics Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp 412.
Instruction Selection, II Tree-pattern matching Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in.
From Cooper & Torczon1 Implications Must recognize legal (and illegal) programs Must generate correct code Must manage storage of all variables (and code)
Improving Code Generation Honors Compilers April 16 th 2002.
Introduction to Optimization Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved.
Wrapping Up Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved.
Introduction to Code Generation Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved.
Instruction Selection Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp 412 at Rice University.
The Procedure Abstraction Part I: Basics Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp 412.
Overview of the Course Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp 412 at Rice University.
Lexical Analysis - An Introduction Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp 412 at.
Lexical Analysis - An Introduction Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp 412 at.
The Procedure Abstraction, Part VI: Inheritance in OOLs Comp 412 Copyright 2010, Keith D. Cooper & Linda Torczon, all rights reserved. Students enrolled.
The Procedure Abstraction, Part V: Support for OOLs Comp 412 Copyright 2010, Keith D. Cooper & Linda Torczon, all rights reserved. Students enrolled in.
Local Register Allocation & Lab Exercise 1 Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp.
Instruction Selection and Scheduling. The Problem Writing a compiler is a lot of work Would like to reuse components whenever possible Would like to automate.
Cleaning up the CFG Eliminating useless nodes & edges C OMP 512 Rice University Houston, Texas Fall 2003 Copyright 2003, Keith D. Cooper & Linda Torczon,
Local Instruction Scheduling — A Primer for Lab 3 — Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled.
Introduction to Code Generation Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp 412 at Rice.
Boolean & Relational Values Control-flow Constructs Comp 412 Copyright 2010, Keith D. Cooper & Linda Torczon, all rights reserved. Students enrolled in.
Instruction Selection, Part I Selection via Peephole Optimization Copyright 2010, Keith D. Cooper & Linda Torczon, all rights reserved. Students enrolled.
Instruction Scheduling Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved.
Intermediate Code Generation CS 671 February 14, 2008.
1 March 16, March 16, 2016March 16, 2016March 16, 2016 Azusa, CA Sheldon X. Liang Ph. D. Azusa Pacific University, Azusa, CA 91702, Tel: (800)
Introduction to Optimization
Local Register Allocation & Lab Exercise 1
The Procedure Abstraction Part IV: Allocating Storage & Establishing Addressability Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights.
Overview of the Course Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp 412 at Rice University.
Local Instruction Scheduling
Lexical Analysis - An Introduction
Introduction to Optimization
Intermediate Representations
Wrapping Up Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp 412 at Rice University have explicit.
Local Instruction Scheduling — A Primer for Lab 3 —
The Procedure Abstraction Part V: Run-time Structures for OOLs
The Procedure Abstraction Part I: Basics
Code Shape III Booleans, Relationals, & Control flow
Instruction Selection, II Tree-pattern matching
Compiler Construction
Intermediate Representations
The Last Lecture COMP 512 Rice University Houston, Texas Fall 2003
Register Allocation Hal Perkins Summer 2004
Introduction to Parsing
Code Shape IV Procedure Calls & Dispatch
Register Allocation Hal Perkins Autumn 2005
Introduction to Parsing
Instruction Selection Hal Perkins Autumn 2005
Overview of the Course Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp 412 at Rice University.
Lecture 15: Code Generation - Instruction Selection
Local Register Allocation & Lab Exercise 1
Introduction to Optimization
Lecture 16: Register Allocation
Lexical Analysis - An Introduction
Copyright 2003, Keith D. Cooper & Linda Torczon, all rights reserved.
8 Code Generation Topics A simple code generator algorithm
Algebraic Reassociation of Expressions COMP 512 Rice University Houston, Texas Fall 2003 P. Briggs & K.D. Cooper, “Effective Partial Redundancy Elimination,”
CPU Structure CPU must:
Target Code Generation
Procedure Linkages Standard procedure linkage Procedure has
Presentation transcript:

Introduction to Code Generation Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp 412 at Rice University have explicit permission to make copies of these materials for their personal use.

Structure of a Compiler A compiler is a lot of fast stuff followed by some hard problems The hard stuff is mostly in code generation and optimization For superscalars, its allocation & scheduling that count O(n) O(n) O(n log n) Scanner Parser Analysis & Optimization words IR IR Instruction Selection asm Instruction Scheduling asm Register Allocation asm ∞ regs ∞ regs k regs Either fast or NP-Complete NP-Complete NP-Complete

Structure of a Compiler For the rest of 412, we assume the following model Selection is fairly simple (problem of the 1980s) Allocation & scheduling are complex Operation placement is not yet critical (unified register set) What about the IR ? Low-level, RISC-like IR called ILOC Has “enough” registers ILOC was designed for this stuff Instruction Selection Instruction Scheduling Register Allocation Analysis & Optimization IR asm  regs k { Branches, compares, & labels Memory tags Hierarchy of loads & stores Provision for multiple ops/cycle

These 3 problems are tightly coupled. Definitions Instruction selection Mapping IR into assembly code Assumes a fixed storage mapping & code shape Combining operations, using address modes Instruction scheduling Reordering operations to hide latencies Assumes a fixed program (set of operations) Changes demand for registers Register allocation Deciding which values will reside in registers Changes the storage mapping, may add false sharing Concerns about placement of data & memory operations These 3 problems are tightly coupled.

The Big Picture How hard are these problems? Instruction selection Can make locally optimal choices, with automated tool Global optimality is (undoubtedly) NP-Complete Instruction scheduling Single basic block  heuristics work quickly General problem, with control flow  NP-Complete Register allocation Single basic block, no spilling, & 1 register size  linear time Whole procedure is NP-Complete

The Big Picture Conventional wisdom says that we lose little by solving these problems independently Instruction selection Use some form of pattern matching Assume enough registers or target “important” values Instruction scheduling Within a block, list scheduling is “close” to optimal Across blocks, build framework to apply list scheduling Register allocation Start from virtual registers & map “enough” into k With targeting, focus on good priority heuristic This slide is full of “fuzzy” terms Optimal for > 85% of blocks

See Morgan’s book for more ILOC examples Code Shape Definition All those nebulous properties of the code that impact performance & code “quality” Includes code, approach for different constructs, cost, storage requirements & mapping, & choice of operations Code shape is the end product of many decisions (big & small) Impact Code shape influences algorithm choice & results Code shape can encode important facts, or hide them Rule of thumb: expose as much derived information as possible Example: explicit branch targets in ILOC simplify analysis Example: hierarchy of memory operations in ILOC (in EaC) See Morgan’s book for more ILOC examples

Code Shape My favorite example What if x is 2 and z is 3? What if y+z is evaluated earlier? The “best” shape for x+y+z depends on contextual knowledge There may be several conflicting options x + y + z x + y  t1 t1+ z  t2 x + z  t1 t1+ y  t2 y + z  t1  z y x Addition is commutative & associative for integers

Code Shape Another example -- the case statement Implement it as cascaded if-then-else statements Cost depends on where your case actually occurs O(number of cases) Implement it as a binary search Need a dense set of conditions to search Uniform (log n) cost Implement it as a jump table Lookup address in a table & jump to it Uniform (constant) cost Compiler must choose best implementation strategy No amount of massaging or transforming will convert one into another