ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES

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Presentation transcript:

ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES 11/22/2018 ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Test Economics: Cost analysis and model fitting

Benefits and Costs of DFT Design and test + / - Fabri- cation + Manuf. Test - Level Chips Boards System Maintenance test Diagnosis and repair Service interruption + Cost increase - Cost saving +/- Cost increase may balance cost reduction 11/22/2018

Clustered defects (VLSI) VLSI Defects Good chips Faulty chips Defects Wafer Unclustered defects Wafer yield = 12/22 = 0.55 Clustered defects (VLSI) Wafer yield = 17/22 = 0.77 11/22/2018

Test Coverage from Fault Simulator Stuck-at fault coverage Vector number 11/22/2018

Measured Chip Fallout Measured chip fallout Vector number 11/22/2018

Model Fitting Chip fallout vs. fault coverage Y (1) = 0.7623 Chip fallout and computed 1-Y (T ) Measured chip fallout Y (T ) for Af = 2.1 and b = 0.083 Stuck-at fault coverage, T 11/22/2018

Computed DL 237,700 ppm (Y = 76.23%) Defect level in ppm Stuck-at fault coverage (%) 11/22/2018