Serial EEPROM (Atmel 24C-512) CENBD 452 Advanced Digital Design Dale Lamb email: dvl104@psu.edu

Uses and Features Non – Volatile memory similar to RAM with the exception that it remembers it’s last state when powered down. Atmel EEPROM Chip provides 524,288 bits of serial electronically erasable data and programmable read-only memory organized as 65,536 words of 8-Bits each. Device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. Chip operates within the constraints of 1.8V min to a maximum voltage of 5.5V Chip has a high reliability up to 100,000 write cycles, Data retention of up to 40 years

PIN Layout Symbol Pin name Vcc Voltage GND Ground A0 to A2 Device Address SDA Serial data input-output SCL Serial clock input WP Write protection

Pin Operations Serial Clock (SCL) – The SCL input is used as a positive edge input into the EEPROM and negative edge clock data output from the device Serial Data (SDA) – The SDA pin is bi directional for serial data transfer. This pin is open-drain driven and may be wired with any number of other open-drain or open-collector devices Device Addresses (A2, A1, A0) – This chip uses the A2 and A1 inputs for hard wire addressing with up to four 512K devices addressed on a single bus system. When the pins are not hardwired the default values for A1 and A0 is zero. The Write Protection Pin (WP) provides hardware data protection. The protection pin also allows normal write operations when connected to ground. During the write cycle the EEPROM becomes non responsive until the write is complete. When the WP is connected to Vcc, the write protection is inhibited. If WP is left unconnected it will be internally pulled to ground. Switching WP to Vcc prior to a write operation leads to a software write protection function.

EEPROM Operations The SDA pin is pulled high with an external device Data on the SDA pin changes only when the SCL drops low. If the SCL is high and data changes this indicates a start condition. A start condition is simply a high-to-low transition of the SDA when the SCL goes high. The SCL going high must precede any other command for a condition to be considered the start condition. A stop condition is a low-to-high transition of SDA with SCL high. After a read command to the EEPROM the stop command places the chip in standby power mode. All addresses and data words are serially transmitted to and from the EEPROM in 8 bit words. The EEPROM sends a zero to acknowledge that it has received a word. This happens during the ninth clock cycle. The memory of an EEPROM chip can be reset on the ninth clock cycle, or when SDA is high while SCL is high, or the creation of a start Condition.

Random vs. Sequential Access Read operations are initiated the same way that the write operations with the exception that the read/write select bit in the device is set to one Random Read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data address word are clocked in and acknowledged by the EEPROM, the control device must generate another start condition. The control then initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The control device then provides the stop condition. Sequential Read is initiated by a random address read. After the control unit receives a data word it responds with an acknowledge. It will continue to increment the data word address and serially clock out data words. When the memory address limit is reached, the data word address will roll over and the sequential read will continue. The read eventually ends when a stop condition is sent from the control unit.

Block Diagram

Data Sheets http://www.atmel.com/atmel/products/prod162.htm