CSCI206 - Computer Organization & Programming Machine Language zyBook: 5.4 Lab 2 & Prelab 3 are due tomorrow!

Positional Number Systems n-th digit base Example: in base 10 (decimal)

Common bases Decimal: b=10, digits={0,1,2,3,4,5,6,7,8,9} Binary: b=2, digits={0,1} Octal: b=8, digits={0,1,2,3,4,5,6,7} Hexadecimal: b=16, digits={0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F}

Conversion Shortcuts from binary Binary to octal: each group of three binary digits gives a complete octal digit Binary to hexadecimal: each group of four binary digits gives a complete hex digit e.g., 111 010 1012 -> 7258 e.g., 3678-> 011 110 1112 e.g., 1 1101 01012 -> 1D516 e.g., 3A416-> 0011 1010 01002

Endianness The order in which bytes are stored in a multibyte word big-endian: stored with the most significant bits first (natural order when read from left to right) little-endian: stored with the least significant bits first (looks weird)

Endian Examples The hexadecimal value 0x01020304 01 02 03 04 04 03 02 Big endian address 01 02 03 04 100 100 101 102 103 byte address Little endian address 04 03 02 01 100 100 101 102 103 byte address

MIPS Endianness ISA Supports either As a result we’ll use both the MIPS simulator we will use uses the host endianness, in our case LITTLE our mips machine uses BIG endian

MIPS Summary 32-bit architecture load-store memory system (RISC) design principle 2: smaller is faster 32-bit architecture load-store memory system (RISC) optimized for the common case 64 possible instructions (Why? How many bits?) 32 registers arithmetic operations have 3 operands 3 registers or 2 registers and one immediate value

32-bit Architecture What does it mean to be 32-bit? 32 bit word size 0xFFFFFFFF RAM What does it mean to be 32-bit? This typically means the CPU operates on 32-bit sized chunks of data (words) Addresses(Pointers) are 32-bits long start of memory 0 end of memory 232-1 = 0xFFFFFFFF

von Neumann code is data but how do we represent instructions? c = text file assembly = text file Need a simple representation to keep the CPU simple

Assembly vs Machine Language 00000000 <main>: 0: 27bdffe0 addiu sp,sp,-32 4: afbf001c sw ra,28(sp) 8: afbe0018 sw s8,24(sp) c: 03a0f021 move s8,sp 10: 3c020000 lui v0,0x0 14: 24440000 addiu a0,v0,0 18: 24050201 li a1,513 1c: 240601e0 li a2,480 20: 0c000000 jal 0 <main> Machine (byte) code Assembly language code (text)

Assembly Language Symbolic representation of machine code easier for humans to write simple translation to machine code (assembler) assembly language also provides pseudo instructions Instructions that don’t actually exist in the ISA but are useful move $t0, $s0 is a pseudo instruction translated to: ____________________?

Concept Data and instructions are both stored as binary data (numbers) in memory.

Machine Language Each (non-pseudo) assembly instruction is given an operation code (opcode) MIPS supports 64 opcodes, how many bits are needed? A single MIPS instruction is 32-bits long classic RISC design CISC processors allow variable length instructions increases decode complexity

MIPS Machine Language a machine instruction always begins with the opcode opcode [31:26] .. 26 bits remain 32-bit instruction

Registers Come next Most instructions operate on registers the JUMP instructions do not! Others access 2 or 3 registers There are 32 registers in MIPS how many bits are needed to specify a register?

MIPS Machine Language Design Principle 3: Good design demands good compromises. Three different types of instructions specified in opcode R-type: registers are operands I-type: registers and immediate value J-type: jump instructions opcode [31:26] reg1 [25:21] reg2 [20:16] reg3 [15:11] opcode [31:26] reg1 [25:21] reg2 [20:16] opcode [31:26]

1. Arithmetic (R-type) instructions 32 bits opcode rs rt rd shift amount function opcode = basic operation (arithmetic = 0) rs = first source register rt = second source register rd = destination register shift amount = used for binary shift instruction function = which arithmetic operation to perform (sent to the ALU) (e.g., add = 0x20, addu = 0x21...

R-type example add $v0, $v0, $a0 6 bits 5 bits opcode rs (source1) rt (source2) rd (dest) shift amount function add $v0, $v0, $a0

R-type example add $v0, $v0, $a0 not used for add, set to 0 opcode rs rd shift amount function add = 0x20 arithmetic = 0 add $v0, $v0, $a0

R-type example add $v0, $v0, $a0 not used for add, set to 0 rs rt rd rs rt rd 0x20 add = 0x20 arithmetic = 0 add $v0, $v0, $a0

R-type example 2 4 0x20 add $v0, $v0, $a0

R-type example add $v0, $v0, $a0 6 bits 5 bits 2 4 0x20 000000 00010 2 4 0x20 000000 00010 00100 00000 100000 add $v0, $v0, $a0

R-type example add $v0, $v0, $a0 ?? (hex value) 6 bits 5 bits 2 4 0x20 2 4 0x20 000000 00010 00100 00000 100000 add $v0, $v0, $a0 ?? (hex value)

R-type example add $v0, $v0, $a0 0x00441020 6 bits 5 bits 2 4 0x20 2 4 0x20 000000 00010 00100 00000 100000 add $v0, $v0, $a0 0x00441020

2. Immediate (I-Type) Instruction R-type is used when there are three operands. Many times we have a constant or immediate operand. In this case that immediate value is included in the instruction.

Immediate (I-Type) Instruction 6 bits 5 bits 16 bits opcode rs rt immediate value Small constants are used frequently by programs I-type instructions encode a 16-bit signed value to be used by the instruction

I-Type example addi $s0, $s1, 40 6 bits 5 bits 16 bits opcode rs rt immediate value addi $s0, $s1, 40

I-Type example addi $s0, $s1, 40 6 bits 5 bits 16 bits opcode rs rt immediate value 8 40 addi $s0, $s1, 40

I-Type example addi $s0, $s1, 40 6 bits 5 bits 16 bits 8 rs rt 40 16 17 addi $s0, $s1, 40

I-Type example addi $s0, $s1, 40 ?? (hex value) 6 bits 5 bits 16 bits 8 17 16 40 001000 10001 10000 0000000000101000 addi $s0, $s1, 40 ?? (hex value)

I-Type example addi $s0, $s1, 40 0x22300028 6 bits 5 bits 16 bits 8 17 001000 10001 10000 0000000000101000 addi $s0, $s1, 40 0x22300028

3. Jump (J-type) instruction This instruction just tells the CPU to fetch the next instruction from a different location. That location is encoded as an unsigned immediate value in the instruction. 6 bits 26 bits opcode instruction address

J-type Example j MAIN ; assume MAIN = 0x400010 6 bits 26 bits opcode instruction address 5 j MAIN ; assume MAIN = 0x400010

J-type Example j MAIN ; assume MAIN = 0x0400010 6 bits 26 bits opcode instruction address 2 j MAIN ; assume MAIN = 0x0400010 0x0400010 is a byte address, but in MIPS instructions must be word aligned. So the lower 2 bits of the byte address must be 00. Therefore we omit them to save space! (making the 26-bit instruction effectively 28-bits!)

J-type Example j MAIN ; assume MAIN = 0x0400010 6 bits 26 bits opcode instruction address 2 0x0100004 j MAIN ; assume MAIN = 0x0400010 removing the lower 2 bits of 0x0400010 is the same as dividing by 4 (shift right by 2), so the encoded value is 0x0100004.

J-type Example j MAIN # assume MAIN == 0x400010 ?? (hex value) 6 bits 000010 0x0100004 j MAIN # assume MAIN == 0x400010 ?? (hex value)

J-type Example j MAIN ; assume MAIN == 0x400010 0x08100004 6 bits 000010 0x0100004 j MAIN ; assume MAIN == 0x400010 0x08100004