Day 17: October 18, 2010 (Energy) Ratioed Logic ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 17: October 18, 2010 (Energy) Ratioed Logic Penn ESE370 Fall2010 -- DeHon

Today Energy and Power Ratioed Gates Data dependence Switching vs. Leakage Energy vs. Delay Ratioed Gates Correctness Performance Power Implications Penn ESE370 Fall2010 -- DeHon

Data Dependent Activity Consider an 8b counter What is activity, a, for: Low bit? High bit? Assuming random inputs (no glitching) Activity at output of nand4? Activity at output of xor4? Penn ESE370 Fall2010 -- DeHon

Total Power Ptot = Pstatic + Psc + Pdyn Pdyn + Psc = a(½Cload+Csc)V2f Ptot ≈ a(½Cload+Csc)V2f+VI’s(W/L)e-Vt/(nkT/q) Penn ESE370 Fall2010 -- DeHon

Slow Down Ptot ≈ a(½Cload+Csc)V2f+VI’s(W/L)e-Vt/(nkT/q) What happens to power contributions as reduce clock frequency? What suggest about Vt? Penn ESE370 Fall2010 -- DeHon

ITRS 2009 Penn ESE370 Fall2010 -- DeHon Year of Production 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (contacted) 54 45 38 32 27 24 21 18.9 16.9 15 13.4 11.9 10.6 9.5 8.4 7.5 Lg: Physical Lgate for High Performance logic (nm) [1] 29 22 20 18 17 15.3 14 12.8 11.7 10.7 9.7 8.9 8.1 7.4 EOT: Equivalent Oxide Thickness (nm) [2] Extended planar bulk 1 0.95 0.88 0.75 0.65 0.55 0.53   UTB FD 0.7 0.68 0.6 0.57 0.54 0.5 MG 0.77 0.67 0.64 0.62 0.59 Channel doping (E18 /cm3) [3] Extended Planar Bulk 3.7 4 4.5 5 5.7 6.6 0.1 Junction depth or body Thickness (nm) [4] Extended Planar Bulk (junction) 13 12 10.5 8.7 8 7.3 UTB FD (body) 7 6 5.5 5.1 4.7 4.3 3.9 MG (body) 7.6 6.4 5.8 4.8 4.2 EOTelec: Electrical Equivalent Oxide Thickness (nm) [5] 1.32 1.26 1.2 1.06 0.85 0.82 1.1 1.08 0.97 0.94 0.9 1.17 1.07 1.04 1.02 0.99 0.93 Cg ideal (fF/mm) [6] 0.76 0.73 0.72 0.71 0.63 0.58 0.47 0.45 0.48 0.42 0.39 0.37 0.35 0.32 0.3 0.28 Jg,limit: Maximum gate leakage current density (kA/cm2) [7] 0.83 1.3 1.4 1.5 1.7 1.9 2.1 2.2 2.5 2.7 2.9 Vdd: Power Supply Voltage (V) [8] P bulk/UTB FD/MG 0.87 0.84 0.81 0.78 0.66 Vt,sat: Saturation Threshold Voltage (mV) [9] 285 289 294 291 295 309 302 221 220 228 232 236 235 206 202 207 209 219 213 231 Isd,leak (nA/mm) [10] Bulk/UTB FD/MG 100 Mobility enhancement factor due to strain [11] 1.8 Effective Ballistic Enhancement Factor, Kbal [12] 1.12 1.19 1.34 1.42 1.59 1.69 1.79 2.01 Rsd: Effective Parasitic series source/drain resistance (Ω-µm) [13] 170 160 140 130 110 120 Id,sat: NMOS Drive Current (µA/µm) [14] 1,210 1,200 1,190 1,300 1,450 1,580 1,680 1,470 1,520 1,670 1,730 1,770 1,830 1,970 1,490 1,630 1,710 1,790 1,860 1,870 2,000 2,060 2,110 2,170 Equivalent injection velocity, vinj (107 cm/s) [15] 0.98 0.86 1.41 1.01 1.11 1.21 1.43 1.53 1.72 1.92 2.09 2.32 Cg fringing capacitance (fF/mm) [16] 0.24 0.25 0.26 0.23 0.17 0.19 0.18 Cg,total: Total gate capacitance for calculation of CV/I (fF/µm) [17] 0.96 0.8 0.61 0.46 Penn ESE370 Fall2010 -- DeHon

ITRS 2009 45nm C0 = 0.045mm × Cg,total High Performance Low Power Isd,leak 100nA/mm 50pA/mm Isd,sat 1200 mA/mm 560mA/mm Cg,total 1fF/mm 0.91fF/mm Vth 285mV 585mV C0 = 0.045mm × Cg,total Penn ESE370 Fall2010 -- DeHon

High Power V=1V Csc = 0 Cload=22C0 ≈ 1 fF = 10-15F (just for simplicity, typically <Cload) Cload=22C0 ≈ 1 fF = 10-15F WN = 2  Ileak = 9×10-9 A P=a(0.5×10-15) freq + 9×10-9 W Penn ESE370 Fall2010 -- DeHon

Compare P=a(0.5×10-15) freq + 9×10-9 W a=0.2 P=10-16×freq + 9×10-9 W For what freqs does leakage power dominate switching power? Penn ESE370 Fall2010 -- DeHon

ITRS 2009 45nm C0 = 0.045mm × Cg,total High Performance Low Power Isd,leak 100nA/mm 50pA/mm Isd,sat 1200 mA/mm 560mA/mm Cg,total 1fF/mm 0.91fF/mm Vth 285mV 585mV C0 = 0.045mm × Cg,total Penn ESE370 Fall2010 -- DeHon

Reduce V What happens as reduce V? Delay? Energy? Static Switching Ptot ≈ a(½Cload+Csc)V2f+VI’s(W/L)e-Vt/(nkT/q) Penn ESE370 Fall2010 -- DeHon

Reduce V (no physical scale) tgd=Q/I=(CV)/I V S×V Id=(mCOX/2)(W/L)(Vgs-VTH)2 Id  S2×Id tgd  tgd /S Penn ESE370 Fall 2010 -- DeHon

Observe Ignoring leakage Penn ESE370 Fall2010 -- DeHon

Energy vs. Power? What do we care about? Battery operated devices? Desktops? Penn ESE370 Fall2010 -- DeHon

Ratioed Logic Penn ESE370 Fall2010 -- DeHon

Note on what about to see Not clear win Should be able to analyze Chance to exercise analysis Kind of thing you want to be able to analyze Pattern should recognize May be a stepping stone to something interesting to come… Penn ESE370 Fall2010 -- DeHon

Idea Building both pull-up and pull-down can be expensive – many gates Seems wasteful to build logic function twice Once in pullup, once in pulldown Large capacitance Penn ESE370 Fall2010 -- DeHon

Idea Maybe only need to build one Build NFET pulldown Exploit high N mobility Penn ESE370 Fall2010 -- DeHon

Ratioed Inverter Does this work? WP=1 WN=1 Penn ESE370 Fall2010 -- DeHon

Ratioed Inverter How do we need to size N to make it work? WP=1 Penn ESE370 Fall2010 -- DeHon

DC Transfer Function Penn ESE370 Fall2010 -- DeHon

Worst-Case Output Drive? WP=1 Penn ESE370 Fall2010 -- DeHon

Noise Margin Tradeoff Impact of increasing (reducing) noise margin? Penn ESE370 Fall2010 -- DeHon

Class stopped here Penn ESE370 Fall2010 -- DeHon

Size for R0/2 drive? Penn ESE370 Fall2010 -- DeHon

Compare Static CMOS Total Transistor Width Input capacitance load Penn ESE370 Fall2010 -- DeHon

Power? Istatic ? Output high? Output low? Ileak Ipmos_on Vdd/(R0/2) -- for our sample case Penn ESE370 Fall2010 -- DeHon

Power Ptot ≈ a(½Cload+Csc)V2f +PlowV2/Rpon +(1-Plow)VI’s(W/L)e-Vt/(nkT/q) Penn ESE370 Fall2010 -- DeHon

How size for R0/2 drive? Penn ESE370 Fall2010 -- DeHon

How size for R0/2 drive? Penn ESE370 Fall2010 -- DeHon

Which Implementation is faster in ratioed logic? Penn ESE370 Fall2010 -- DeHon

Illustrates Preferred gate changes Penn ESE370 Fall2010 -- DeHon

How size for R0/2 drive? K-input nor Penn ESE370 Fall2010 -- DeHon

When better than CMOS nor-k? Better = smaller, lower input capacitance Penn ESE370 Fall2010 -- DeHon

Admin Project Andre office hours Tuesday 4:30pm Hope you got a chance to try out many things this weekend Due Friday Andre office hours Tuesday 4:30pm Penn ESE370 Fall2010 -- DeHon

Ideas Energy-Delay tradeoff: Et2 There are other logic disciplines We have the tools to analyze Ratioed Logic Tradeoff noise margin for Reduced area? Capacitive load? Dissipates static power in one mode Penn ESE370 Fall2010 -- DeHon