Injection Locked Clocking with Ring Oscillators

Slides:



Advertisements
Similar presentations
Entropy Extraction in Metastability-based TRNG
Advertisements

Slide 1 Bayesian Model Fusion: Large-Scale Performance Modeling of Analog and Mixed- Signal Circuits by Reusing Early-Stage Data Fa Wang*, Wangyang Zhang*,
The Cost of Fixing Hold Time Violations in Sub-threshold Circuits Yanqing Zhang, Benton Calhoun University of Virginia Motivation and Background Power.
Digital Integrated Circuits© Prentice Hall 1995 Timing ISSUES IN TIMING.
June 20 th 2004University of Utah1 Microarchitectural Techniques to Reduce Interconnect Power in Clustered Processors Karthik Ramani Naveen Muralimanohar.
1 A Variation-tolerant Sub- threshold Design Approach Nikhil Jayakumar Sunil P. Khatri. Texas A&M University, College Station, TX.
6/16/20151 On Designing Improved Controllers for AQM Routers Supporting TCP flows By C.V Hollot, Vishal Mishra, Don Towsley and Wei-Bo Gong Presented by.
Circuit Performance Variability Decomposition Michael Orshansky, Costas Spanos, and Chenming Hu Department of Electrical Engineering and Computer Sciences,
Processing Rate Optimization by Sequential System Floorplanning Jia Wang 1, Ping-Chih Wu 2, and Hai Zhou 1 1 Electrical Engineering & Computer Science.
Leakage Efficient Chip-Level Dual-Vdd Assignment with Time Slack Allocation for FPGA Power Reduction Yan Lin and Lei He EE Department, UCLA Partially supported.
- 1 - Interconnect modeling for multi-GHz clock network Special interconnect structure –Wires highly optimized with VDD/GND shields –Wide lines split into.
DELAY INSERTION METHOD IN CLOCK SKEW SCHEDULING BARIS TASKIN and IVAN S. KOURTEV ISPD 2005 High Performance Integrated Circuit Design Lab. Department of.
1 Process-Variation Tolerant Design Techniques for Multiphase Clock Generation Manohar Nagaraju +, Wei Wu*, Cameron Charles # + University of Washington,
S. -L. Jang, Senior Member, IEEE, S. -H. Huang, C. -F. Lee, and M. -H
Silicon Solutions for the Real World 1 AID-EMC Automotive IC Design for Low EMC Review Meeting 29 augustus 2006 VILVOORDE.
An Efficient Clustering Algorithm For Low Power Clock Tree Synthesis Rupesh S. Shelar Enterprise Microprocessor Group Intel Corporation, Hillsboro, OR.
MICAS Department of Electrical Engineering (ESAT) Design-In for EMC on digital circuit October 27th, 2005 AID–EMC: Low Emission Digital Circuit Design.
Simulation Of A Cooperative Protocol For Common Control Channel Implementation Prepared by: Aishah Thaher Shymaa Khalaf Supervisor: Dr.Ahmed Al-Masri.
Power Management for Nanopower Sensor Applications Michael Seeman EE 241 Final Project Spring 2005 UC Berkeley.
Delay Locked Loop with Linear Delay Element
On-Chip Sensors for Process, Aging, and Temperature Variation
1ISPD'03 Process Variation Aware Clock Tree Routing Bing Lu Cadence Jiang Hu Texas A&M Univ Gary Ellis IBM Corp Haihua Su IBM Corp.
1 Channel Equalization for STBC- Encoded Cooperative Transmissions with Asynchronous Transmitters Xiaohua (Edward) Li, Fan Ng, Juite Hwu, Mo Chen Department.
EE415 VLSI Design THE INVERTER [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
Results Section of Hick’s Thesis on “Modeling Greenhouse Gas Emissions from Conventional Wastewater Treatment Plants in South Carolina”
Delay-based Spread Spectrum Clock Generator Subramaniam Venkatraman Matthew Leslie University of California, Berkeley EE 241 Final Presentation May 9 th.
1 Status report on the LAr optical link 1.Introduction and a short review. 2.The ASIC development. 3.Optical interface. 4.Conclusions and thoughts Jingbo.
May 2006Andreas Steininger1 D istributed A lgorithms for R obust T ick S ynchronization.
Status of ATF2 linear collider focus prototype emphasizing France-China joint contributions Philip Bambade Laboratoire de l’Accélérateur Linéaire Université.
The Structuring of Systems Using Upcalls David D. Clark (Presented by John McCall)
Yanqing Zhang University of Virginia On Clock Network Design for Sub- threshold Circuitry 1.
Supporting Low Power Operation
Gopakumar.G Hardware Design Group
Power-Optimal Pipelining in Deep Submicron Technology
AIDA design review 31 July 2008 Davide Braga Steve Thomas
Asynchronous Primitives in CML
High-Speed Stochastic Circuits Using Synchronous Analog Pulses M
Principios de Comunicaciones EL4005
Digital readout architecture for Velopix
Progressive Computation of The Min-Dist Optimal-Location Query
On the Relevance of Wire Load Models
Control Design and Analysis of Chained Systems
Overview of the project
OPS - Energy Harvesting
Pablo Abad, Pablo Prieto, Valentin Puente, Jose-Angel Gregorio
Y. Irie, KEK for the LOI collaboration
Andrew B. Kahng and Xu Xu UCSD CSE and ECE Depts.
Revisiting and Bounding the Benefit From 3D Integration
Jason Cong, David Zhigang Pan & Prasanna V. Srinivas
Two-phase Latch based design
CARP: Compression Aware Replacement Policies
CMOS VLSI Design Chapter 13 Clocks, DLLs, PLLs
VLSI Project Presentation
Avogadro-Scale Engineering:
CMOS VLSI Design Chapter 13 Clocks, DLLs, PLLs
Title: An Adaptive Queue Management Method for Congestion Avoidance in TCP/IP Networks Presented By: Frank Posluszny Vishal Phirke Matt Hartling 12/31/2018.
Day 21: October 29, 2010 Registers Dynamic Logic
Post-Silicon Calibration for Large-Volume Products
Reducing Clock Skew Variability via Cross Links
Vishwani D. Agrawal James J. Danaher Professor
Multiport, Multichannel Transmission Line: Modeling and Synthesis
An Energy Efficient Two-Phase Clocking Scheme
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy
UNIVERSITY OF MASSACHUSETTS Dept
UNIVERSITY OF MASSACHUSETTS Dept
Pingli Huang and Yun Chiu
Chapter 3b Leakage Efficient Chip-Level Dual-Vdd Assignment with Time Slack Allocation for FPGA Power Reduction Prof. Lei He Electrical Engineering Department.
Jason Cong, David Zhigang Pan & Prasanna V. Srinivas
Physics performances of baseline target design (Solution #5)
Lecture 22: PLLs and DLLs.
Presentation transcript:

Injection Locked Clocking with Ring Oscillators Rachel Nancollas and Suchit Bhattarai

Motivation: Problems with Clocking Energy Skew Source: Lin Zhang, PhD thesis Is Injection Locked Clocking (ILC) the solution?

Injection Locked Clocking source: Lin Zhang, et al. Weak injecting signal locks local oscillator to global frequency This means the previous buffers can be smaller

Current Implementations source: Lin Zhang, et al. Current oscillator designs LC Tanks Complex digital feedback (MDLLs) Proposal: ILC with ring oscillators source: H. Ng, et al.

Current Starved Ring Oscillators

System Overview Conventional Clocking Network Injection Locked Ring Oscillator Clocking Network

Analytical Optimization Optimize EDP Variables Stage 1: number of stages (N), fanout (fn) Stage 2: number of stages (M), fanout (fm) Injection Buffer Size (C_inj) Process: Optimize EDP for stage 1 and 2: N, M, fn, fm as a function of C_inj Find total EDP: choose C_inj to get min EDP

Optimization Results Energy is similar ILRO has higher delay optimization pushes fanout to later stages pays energy of slave oscillator Conclusion: ILRO doesn't look good

Simulation Results master ILRO conventional

Interconnect Variations Varied interconnect by 10% Conventional ~ 4% delay variation ILRO ~ 2% delay variation Result: ILRO is more tolerant to interconnect variation

Conclusions We developed a model for optimal sizing of ILRO clock trees ILROs are less energy efficient and more prone to skew than conventional clock networks ILROs may be more tolerant to interconnect variations Result for ILC: still no small area oscillators appropriate for digital systems