EE201C Modeling of VLSI Circuits and Systems Final Project Prof. Lei He Assistant: Fang Gong gongfang@ucla.edu

Process Variation Process Variation becomes larger with technology scaling Larger Variations lead to lower Yield Rate Yield Rate is defined as It is significant to estimate and further optimize the yield rate considering process variation!

SRAM reading failure SRAM 6T Cell considering Reading Failure td ΔV Initially, BL and BLB are pre-charged to ‘1’ (high voltage). When reading the SRAM cell, the WL becomes ‘1’, and hold for a while. When WL becomes ‘1’, the BLB starts to discharge from high voltage, and produces a voltage difference ΔV between it and BL. The time for BLB to produce a large enough ΔV is td. If td is larger than the threshold, this leads to an reading failure.

SRAM writing Failure SRAM 6T Cell considering Writing Failure td Initially, BL is pre-charged to ‘1’ (high voltage) and BLB is ‘0’. When writing the SRAM cell, the WL becomes ‘1’, and hold for a while. When WL becomes ‘1’, the BLB starts to increase to high voltage and BL starts to discharge to low voltage. The time for BLB becomes larger than BL is td. If td is larger than the WL hold time, this leads to an writing failure.

Yield Estimation for SRAM Yield Rate Estimation for SRAM Cell Variational case Nominal case The threshold voltage (Vth) and Channel Length (Leff) can be derivate from the nominal value in the design stage due to process variation. The variable parameters (Vth, Leff) can change the discharge speed at BLB, and lead to reading failure. The yield constraint can be given as: At the time-step Tmax, the voltage difference between BL and BLB should be larger than. ΔVthreshold

Yield Optimization for SRAM Yield Optimization by changing nominal values Take two variable parameter case as an example rectangular is the box [p1min, p1max]×[p2min, p2max] each parameter can change within its feasible range determined by process technology. The nominal parameters can lead to successful performance. As the parameters move away from the design point, the circuit's performance also changes away from its nominal value. there exists a region around the nominal design point where the performance remains acceptable It is possible to improve the yield rate by choosing optimal nominal values.

Variable Parameter Specification There are four (independent) variable parameters: M1 Vth and Leff (Nominal Value: Vth = 0.2607V, Leff = 0.1um) M2 Vth and Leff (Nominal Value: Vth = 0.2607V, Leff = 0.1um) They have variations of Gaussian distributions The [min, max] and variation (3σ) for each parameters are: Vth: min = 0.2V, max = 0.5V, 3σ=30% of nominal value Leff: min = 0.095um, max = 0.105um, 3σ=10% of nominal value Note: nominal values for other invariable parameters can be found in provided files.

Performance Constraints Performance Constraints should be satisfied at the same time: (1) Reading and Writing Failure: Reading: voltage difference between BL and BLB should be larger than 164.3mV at time step 10ps. Writing: voltage at BLB node should be larger than voltage at BL node at time step 6.9ps (2) The Power Consumption at the nominal point should be smaller than initial design. (3) The Area at the nominal point should be smaller than initial design The optimal design should have largest Yield rate (considering process variations), and minimum power consumption and area. Yield rate is the most important performance constraint. Efficiency is also Important, the CPU Rum-Time should be kept lowest.

Baseline Algorithm (1) The straightforward way is to do exhaust-search in the design space. Step 1: generate sample sequences for all variable parameters with QMC M2-Leff(nm) M1-Leff(nm) M1-Vth(V) M2-Vth(V) Leff (nm)

Baseline Algorithm (2) Step 2: Generate SPICE Net-list file to do MC simulations.

Baseline Algorithm (3) Success Sampling Step 3: Parse the SPICE output to extract the voltage at 10ps, and power consumption. Step 4: Calculate the Yield Rate with performance constraint. Step 5: Select the optimal design point by comparing the Yield Rate, Power and Area. Fail Sampling

Baseline Algorithm (4) – Experiment Table I. Nominal Parameter Comparison Mn1 Leff (m) Mn1 Vth (V) Mn2 Leff (m) Mn2 Vth (V) Initial Design 1e-07 0.2607 Optimal Design 9.5e-8 0.35 0.21 Table II. Performance Comparison Power (W) Area(m2) Voltage (mV) Yield Initial Design 8.9877e-06 1.8813e-013 164.2677 0.534 Optimal Design 8.8416E-06 1.2918e-013 163.5771 0.996 Above Optimal Design only considers Reading Failure, and will be updated soon! Note: In this case, I choose the sampling with largest yield rate which has smaller power consumption and smaller area than initial design. You may find better sampling than the one shown here.

Final Project Description Now, It is your turn to obtain the optimal design by choosing optimal nominal values for variable parameters and considering following constraints at the same time: (1) Yield Rate: With the optimal nominal values, the yield rate should be maximum considering both reading and writing failures. (2) Power Consumption: The optimal design should have smaller Power Consumption than initial design. (3) Area: The optimal design should have smaller Area than initial design. (4) Run-Time: PLEASE use as LESS Monte Carlo simulations as possible. Note: Please report all these performances in your report, and explain why your method can be efficient and accurate.

Good Luck! Grading Extra Credit: The person who get the best optimized results can get extra credit for the final project. (weighted sum: 50% for ranking of yield rate, 20% for power, 20% for area, 10% for ranking of run time) Good Luck!