ECAL electronics schedule

Slides:



Advertisements
Similar presentations
José C. Da Silva OFF DETECTOR WORSHOP, April 7, 2005, Lisboa SLB and DCC commissioning for 904.
Advertisements

CPT Week, Nov 2003, B. Paul Padley, Rice University1 CSC Trigger Status, MPC and Sorter B. Paul Padley Rice University November 2003.
Endcap Muon meeting: UC Davis, Feb , 2005 J. Hauser UCLA 1 TMB and RAT Status Report Outline: Current status of TMB and RAT boards Noise measurements.
2 October 2003Paul Dauncey1 Paris Summary Part 2 and Status of UK Electronics/DAQ Paul Dauncey Imperial College London, UK.
RAL, 25-Jan-2005Nigel Watson / CCLRC-RAL PPD CALICE Calorimetry for LC  Physics motivation  Calorimetry  Design Considerations  CALICE  Status  Future.
28 August 2002Paul Dauncey1 Readout electronics for the CALICE ECAL and tile HCAL Paul Dauncey Imperial College, University of London, UK For the CALICE-UK.
RBX Integration Review Dec 18, Readout Integration Lab 5 Jim Freeman Overview Dec 18, 2001.
4 Dec 2001First ideas for readout/DAQ1 Paul Dauncey Imperial College Contributions from all of UK: result of brainstorming meeting in Birmingham on 13.
Calice ECAL Readout Hardware Status report Adam Baird ECAL Meeting 26 Sept 2003 LLR-Ecole Polytechnique.
LCWS Apr 2004Paul Dauncey - CALICE Readout1 CALICE ECAL Readout Status Paul Dauncey For the CALICE-UK electronics group: A. Baird, D. Bowerman,
29 January 2004Paul Dauncey - CALICE DAQ1 UK ECAL Hardware Status David Ward (for Paul Dauncey)
10 th November 2004Daniel Bowerman1 Dan Bowerman Imperial College Calice Meeting - UCL 10 th November 2004 Electronics Status For the Imperial, Manchester,
2 April 2003Paul Dauncey - CALICE DAQ1 First Ideas For CALICE Beam Test DAQ Paul Dauncey Imperial College London, UK for IC, Manchester, RAL, UCL.
Status and planning of the CMX Philippe Laurens for the MSU group Level-1 Calorimeter Trigger General Meeting, CERN May 24, 2012.
21 January 2003Paul Dauncey - UK Electronics1 UK Electronics Status and Issues Paul Dauncey Imperial College London.
John Coughlan CMS Week Mar FED Update FED Production Status Transition Card.
14 Sep 2005DAQ - Paul Dauncey1 Tech Board: DAQ/Online Status Paul Dauncey Imperial College London.
CSC EMU Muon Sorter (MS) Status Plans M.Matveev Rice University August 27, 2004.
© Imperial College LondonPage 1 CERC Front End FPGA Development by Osman Zorba 12 May 2004 O. Zorba CALICE 12/05/2004.
John Coughlan Tracker Week Feb FED Status FED Production Status Transition Card.
CMX status and plans Yuri Ermoline for the MSU group Level-1 Calorimeter Trigger Joint Meeting CERN, October 2012,
Status and planning of the CMX Wojtek Fedorko for the MSU group TDAQ Week, CERN April , 2012.
1234 Dec Jan Feb 2007 Delivery of 500 MPPCs MPPC numbering Mass check MPPC soldering WLSF megastrip source scan ACFA Shipping Feb-14.
FED Overview VME-FPGA TTCrx BE-FPGA Event Builder Buffers FPGA Configuration Compact Flash Power DC-DC DAQ Interface 12 Front-End Modules x 8 Double-sided.
Status of shaper prototype production B.G. Cheon (Hanyang U)‏ Dec. KEK 1 st open meeting of the Super KEKB Collaboration.
FDR of the End-cap Muon Trigger Electronics 1/Mar./04 1 Hi-pT Board Hi-pT ASIC Board Type Endcap-wire Endcap-Strip Forward Chikara Fukunaga (TMU)
25 Feb 2005Paul Dauncey1 TB Review: DAQ Paul Dauncey Imperial College London For Imperial, RAL, UCL.
CMX Hardware Overview Chip Brock, Dan Edmunds, Philippe Yuri Wojciech Michigan State University 19-May-2014.
8 Feb 2008Paul Dauncey1 Plans for FY08/09 Paul Dauncey.
1 October 2003Paul Dauncey1 Mechanics components will be complete by end of year To assemble ECAL, they need the VFE boards VFE boards require VFE chips.
Tracker Week October CCLRC, Rutherford Appleton Laboratory, Oxon, UK Imperial College, London, UK Brunel University,
1 ME1/1 ODMB Production Readiness Review: Schedule and Budget Darien Wood Northeastern University For the ME1/1 Electronics Project.
5 February 2003Paul Dauncey - Calice Status1 CALICE Status Paul Dauncey Imperial College London For the CALICE-UK groups: Birmingham, Cambridge, Imperial,
LCWS Apr 2004Paul Dauncey - CALICE Readout1 CALICE ECAL Readout Status Paul Dauncey For CALICE-UK electronics group: A. Baird, D. Bowerman, P. Dauncey,
Xenon Detector Installation schedule Satoshi MIHARA.
FEE Electronics progress Mezzanine layout progress FEE64 progress FEE64 initial testing Test mezzanine. A few of the remaining tasks 2nd October 2009.
11 October 2002Paul Dauncey - CDR Introduction1 CDR Introduction and Overview Paul Dauncey Imperial College London.
4 November 2002Paul Dauncey - Electronics1 UK Electronics Status Paul Dauncey Imperial College London.
Dec
ECAL Plenary 27/2/07 D.J.A. Cockerill - RAL 1 Status of the CMS ECAL Endcaps ECAL Plenary, 27 Feb 2007 D Cockerill  VPTs  Electronics and Integration.
FEE Electronics progress PCB layout progress VHDL progress in TBU Prototype fixture for software 9th June 2009.
CMS-UK Oversight Committee 17/11/06 D.J.A. Cockerill - RAL 1 The CMS Electromagnetic Calorimeter UK Responsibilities Procurement and testing of VPTs Design.
ECAL electronics schedule JFMAMJJASONDJFMAM Prototype 2 boards Design Layout Fabrication and assembly Testing, including VFE prototype tests Production.
DAQ / Trigger Card for HCAL SLHC Readout E. Hazen - Boston University
The SuperB EMC Front End electronics Prototypes
Jan 2016 Solar Lunar Data.
CSC EMU Muon Port Card (MPC)
Combined SR/SP UF Fits all of previous SP board logic! Main FPGA
SCHEDULE Nov 1st - Assembly Table Complete
10/month is the present production rate 2 FTE + sporadic contributions
C. de La Taille IN2P3/LAL Orsay
CDR Project Summary and Issues
CALICE/EUDET Electronics in 2007
UK ECAL Hardware Status
CMX Status and News - post PRR -
CC DEVELOPMENT PROGRESS and SCHEDULE

CMX scope and functionalities
Trigger issues for the CALICE beam test
FEE Electronics progress

RPC FEE The discriminator boards TDC boards Cost schedule.
DCM II DCM II system Status Chain test Schedule.
PLANNING LOOKING AHEAD…. Long Term Goals (Assigned to…)
Text for section 1 1 Text for section 2 2 Text for section 3 3
Text for section 1 1 Text for section 2 2 Text for section 3 3
Text for section 1 1 Text for section 2 2 Text for section 3 3
Text for section 1 1 Text for section 2 2 Text for section 3 3
CALICE(-UK) Status Paul Dauncey 7 Oct 2004 Paul Dauncey.
We are working on developing “cheap” RTD monitoring channels for the CMS Phase-2 requirements. The channels will provide the complete readout for 4-wire.
Presentation transcript:

ECAL electronics schedule 2003 2004 J F M A S O N D Prototype 2 boards Design Layout Fabrication and assembly Testing VFE PCB tests Production 9 boards Redesign Testing, including Paris system cosmic tests DESY beam test

ECAL prototype detailed schedule Oct Nov Dec Jan Feb Week 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 General VME tests Imperial Readout board VME definition Manchester Readout board J0/J2 pin definition RAL/UCL Crate check and backplane wireup RAL JTAG tests Readout board FE FPGA Chipscope tests RAL/Imperial Readout board BE FPGA tests RAL/UCL/Man VFE PCB tests Paris Readout board VME tests