Design and Test for Lumped Scheme of WCDA Readout Electronics Good afternoon, I’d like to introduce our work on the design and test for lumped scheme of WCDA readout electronics Hao Xinjun Key Laboratory of Technologies of Particle Detection & Electronics，Chinese Academy of Sciences 2018/11/23

Outline Introduction Design of readout electronics Test results and future works In my presentation, a brief background of the experiment is introduced first. Then the design and test of our readout electronics is talked in detail 2018/11/23

Outline Introduction Design of readout electronics Test results and future works 2018/11/23

Water Cherenkov Detector Sensitive to cosmic gamma rays Maintaining the all-sky, high-duty-factor capabilities of an EAS array 4 ponds each with the area of 2.25x104m2 Each will be filled with purified water 900 PMTs will be deployed under the water of each pond For a total of 3600 PMTs and corresponding readout electronics 8”PMT such as Hamamatus R5912 is the candidate type As we know, a total of 3600 PMTs will be deployed in the WCDA, distributed in the area of ninety thousands square meters. 2018/11/23 4

The Requirement of Electronics Digitalizing the accurate arrival time of the selected showers Both the timing and pulse height of each PMT is important 1ns time resolution for leading edge time measurement A wide dynamic range of 1~4000 PEs for pulse height measurement A trigger decision must be made to select showers The electronics is required to digitalize the accurate arrival time of the selected showers, with the resolution of better than 1ns, and the pulse height with the dynamic range of 1~4000 PEs. Also the trigger decision, the clock distribution and signal propagation are essential, for the large scale of the ponds. Distributing the large number of signals over the long distance (>100m) is an issue 2018/11/23 5

Specification of readout electronics Design requirements Index Time measurement LSB 1ns Time measurement RMS <0.5ns Dynamic rang of time measurement 2us Internal time of two hits 25ns Charge measurement precision 10%@SPE 5%@4000PE Dynamic rang of charge measurement SPE~4000PE (about 0.8mV~3.2V) Trigger readout window This is the list of the requirements 2018/11/23 6

Outline Introduction Design of readout electronics Test results and future works Now I will talk about the design of the electronics 2018/11/23

Lumped architecture 2018/11/23 The conventional way is the lumped architecture. A cable from each PMT carrying the PMT signal connects to the pre-amplifier. The pre-amplifier then drives the amplified signal to the digitalization module located in the counting house, where the time and charge measurement functions are performed. The fidelity for the fast PMT pulses will be critical. So the cable should be of order 100 meters long and not without loss at high frequencies. Since the attenuation is a function of the bandwidth of the transmitted signal, the details of the cable construction and the cable length. The common “broadband” cables demonstrate the serious attenuations over 100 meters. As an example, the right figure shows a PMT pulse (red) and the same pulse (blue) after traveling 100 m on coaxial cable RG58. Note the loss of amplitude and the slowing of the front and rear edges in the lower trace, we can draw that the loss of high-frequency signal strength would seem a serious problem for getting the required accurate timing from the PMT signals. We will need to optimize in a multi-dimensional space including the cable mass, transmission quality and cost. 2018/11/23 8

Digitalization in Lumped Architecture Similarly with Daya Bay Experiment’s electronics, except that the dual-gain Pre-amplifier is attached Two shaping and ADC circuits for 1 PMT channel, congruous with the Pre- amplifiers Digitalization by high speed (40MSPS) ADC to find the peak of the shaped waveform Fast discriminator provides the arriving time of the pulse, recorded by TDC, and fed to the trigger logic In our lumped design, the process similarly with Dayabay Experiment’s electronics is adopted, except that the additional Pre-amplifier is attached. 2018/11/23 9

Charge Measure Solution The wide dynamic range (1~4000PE), and high charge measurement resolution, are expected in this scheme The amplified signal is fed to the CR-(RC)4 shaping circuits with different gain parameters The simulation shows error of lower than 4% can be achieved with the ADC sampling speed of 40MHz The shaping circuits need to be characterized carefully The 12-bit ADCs are employed to sampling these two signals at a speed of 40MSPS, for the peak finding algorithm Fine range: 1－85PE, Coarse range: 80－4000PE The CR-(RC)4 shaping circuits and peak searching strategy are designed for the charge measurement. 2018/11/23

Time Measure Solution 2018/11/23 A fast discriminator generates the timing pulse The threshold is defined by a DAC set via VME interface The leading edge of the output represents the arrival time of the signal The TDC is built in a high-performance FPGA A coarse counter and the strategy of quadrature clock sampling are designed to achieve the time resolution of 0.893ns (0.625ns with quadrature clock of 400 MHz) Peak searching and buffer logic are also built in the same FPGA And a fast discriminator provides the arriving time of the pulse, recorded by TDC, and fed to the trigger logic. All the TDC and peak searching logic are built in a single high performance FPGA. 2018/11/23

Trigger Trigger type： N-trigger ：The number of fires change from >=N to <N 2-tirgger：2 PMT fire（P:1/1000） 1-trigger：1 PMT fires（P:1/10000） External Trigger Internal Trigger（100Hz adjustable） All the trigger types have been implemented in FPGA and can be switched by configure the corresponding register. Trigger signal is delayed to ensure that all T/Q data have been written into Ram when trigger is valid. Five types of trigger are designed in FPGA and can be switched by configure the corresponding register. 2018/11/23

Prototype Array According to the schedule, a prototype array will be built beside the ARGO hall. 2018/11/23 13

Readout electronics for prototype of WCDA Preamplifier： dual gain fast preamplifier Digital processing board： TDC and QTC of 9 PMTs、 Trigger and data readout through VME bus And here are the readout electronics for the prototype array. It consists of Nine preamplifiers and one digital processing board. 2018/11/23

Pre-Amplifier Due to the wide dynamic range, the dual gain pre-amplifier is essential High gain for small signal (especially for S.P.E) Low gain for big signal (~4000 P.E.) The overlap between the two gain is taken into account Differential cable is better in noise rejection, but worse in bandwidth The custom-built coaxial cable, the same with in KM2A electronics, is the candidate cable A total of 4 versions have been made before its determination. Problems of linearity, noise, EMI and signal transmission are solved through the design of these versions. Due to the wide dynamic range, the dual gain pre-amplifier is essential, of which the high gain is for small signal and low gain for signal with high amplitude. The pre-amplifier will connect the digitalization board via two custom-built coaxial cables, which are the same with in KM2A electronics. 2018/11/23 15

Digital processing board (DPB) Main features: Time measurement of 9 PMTs Charge measurement of 10 PMTs ( include one used for calibration) 5 modes of trigger Online FPGA reconfig GPS (configures and receives data from GPS module) Temperature VME 9u module Chained block transfer (CBLT) The digital processing board deals with the time and charge measurement of 9 PMTs, the generator of trigger and data readout. 2018/11/23

Diagram of data readout This is the diagram of data readout. There are 3 level buffers in the build of data. 3 level buffers are include 2018/11/23

Outline Introduction Design of readout electronics Test results and future works Here are some of test results of the electronics. 2018/11/23

Photo of electronic system PMT pulse before and after shaping DPB The whole electronics system has been tested after the fabrication of the 9U VME digitalization boards. preamplifier 2018/11/23

Joint test with PMTs and DAQ in IHEP preamplifier DPB Darkroom 100m cable DAQ software PMT And the joint test with PMTs and DAQ was carried in IHEP, at the beginning of this year. Joint Test with PMTs and DAQ works well. However, there are some bugs in FPGA logic. 2018/11/23

Test of preamplifier 2018/11/23 Board 1 2 3 4 5 6 8 9 10 11 Channel 2 low gain Gain = 1.029 INL <= 0.73% Channel 2 high gain Gain = 26.18 INL <= 1.23% To evaluate the performance of preamplifiers, pulse with large dynamic range is needed, and it is obtained by the attenuator. Gain and integral non-linearity are tested. Table at the bottom shows the test results of ten board. The mean of high gain is 26.2, and the low gain is almost the unity-gain. Board 1 2 3 4 5 6 8 9 10 11 Gain (H) 25.77 26.18 26.62 26.55 26.02 26.17 26.47 25.91 26.41 25.95 Gain (L) 1.02 1.029 1.018 1.05 1.06 1.09 1.017 0.993 1.04 INL (H) 0.0104 0.0073 0.0062 0.0168 0.0116 0.0178 0.0077 0.0082 0.0079 0.0084 INL (L) 0.088 0.0123 0.011 0.0094 0.0134 0.0159 0.0109 0.0106 0.014 0.0108 2018/11/23

Scheme of TDC test Test method：Signal generator AFG3251 output a periodic pulse ,TDC record a time stamp when the leading edge of the pulse is detected. Then Time interval is obtained by making the difference of two consecutive time stamp. In the test of TDC, a time stamp is generated when the leading of pulse is detected. Time interval is obtained by making the difference of two consecutive time stamp, and all the test result is deduced from these time intervals. 2018/11/23

Result of TDC 2018/11/23 DNL < 0.022LSB INL < 0.02 LSB LSB = 0.893ns (two channels implemented) Channel LSB = 0.893ns LSB = 0.625ns DNL(LSB) INL(LSB) 1 0.0658 0.0627 0.0693 0.0499 2 0.0472 0.0449 0.0871 0.0606 3 0.0425 0.0415 0.0759 0.0510 4 0.0520 0.0533 0.0725 0.0479 5 0.0428 0.0437 0.0734 0.0781 6 0.0461 0.0495 0.0792 0.0722 7 0.0541 0.0542 0.0623 0.0711 8 0.0346 0.1013 0.1122 9 0.0492 0.0549 0.0762 0.0877 We use code density method to obtain the differential and integral non-linearity of TDC. The amount of samples is larger than ten million. As are shown in the table ,The DNL and INL of nine channels under all conditions are less than 12 percents of LSB. The curve of standard deviation very with time interval is shown in the right bottom figure, the maximum standard deviation is less than half a LSB DNL and INL of 9 channel TDC implemented in FPGA Count on each bin 2018/11/23

Scheme of charge measurement test (electronics) To ensure the charge of tested signal, A negative pulse with 20ns width is used as the PMT signal. The amplitude of the pulse is -2000mv. S.P.E (gain = 2*10^6) is obtained by attenuates the pulse by a factor of 68dB. In the test of charge measurement, we input an known negative pulse into the preamplifier, and then 100 meter coaxial cable, and finally the DPB. 2018/11/23

Charge measurement（electronics） SPE： σ = 1.79 LSB mean = 20.3 LSB σ/ mean = 8.79% 85 PE： σ = 12.34 LSB mean = 1825 LSB σ/ mean = 0.68% High Gain (channel 2) 80 PE： σ = 1.76 LSB mean = 33.80 LSB σ/ mean = 5.20% 4000 PE： σ = 10.36 LSB mean = 1815 LSB σ/ mean = 0.57% Low Gain (channel 2) And here are the test results. Ratios of standard deviation and mean value between the sub-range of dual gain are measured. The total dynamic range is about four thousand, and can be enlarged to about 15000 by adjusting the input bias voltage of ADC. 1 2 3 4 5 6 7 8 9 S.PE (High gain) 9.52% 8.79% 10.6% 9.46% 8.72% 10.06% 9.63% 8.95% 10.05% 85PE (High gain) 0.47% 0.68% 0.59% 0.62% 0.67% 0.39% 0.81% 0.74% 80PE (Low gain) 6.03% 5.2% 2.80% 3.03% 4.7% 6.15% 6.65% 5.15% 5.60% 4000PE (low gain) 0.32% 0.57% 0.36% 0.50% 0.58% 0.51% 0.49% 0.54% channel Q Current dynamic range is about 4000, and can be enlarged to about 15000 by adjusting the Input bias voltage of ADC 2018/11/23

S.P.E measurement 2018/11/23 AFG3252 output two pulses， one for LED and the other is synchronized with the PMT signal (after preamplifier and 100m cable). The synchronous signal and PMT signal are fed Into two high channel, and then hit signal generated by the syn- chronous signal is used as the start flag of peak-finder. Here we test the S.PE of PMT, The dual channel signal generator output two synchronized pulse, one for driving the LED, and one as start of peak-finder. By doing this, we count only these Signals produced by LED. 2018/11/23

S.P.E measurement Noise of LED just before PMT pulse brought difficulty of S.P.E measurement the noise just before PMT pulse is very big, and brought difficulty of Single PE measurement. PMT signal and Sync pulse 2018/11/23

S.P.E measurement Histogram of charge (with pulse of 2.95v on LED) Here is the test result, as we can see, the spectral of Single PE is observed but the Peak-valley ratio is very low. Histogram of charge (with pulse of 2.95v on LED) Histogram of charge (with pulse of 2.85v on LED) Histogram of charge (with pulse of 2.65v on LED) Histogram of charge (with pulse of 2.75v on LED) Histogram of charge (with no voltage on LED) 2018/11/23

Future work 2018/11/23 S.P.E measurement still has some work to do Logic bugs in FPGA need to be fixed Joint test with WCDA prototype array in Yangbajing 2018/11/23

Thanks！ That’s all, thanks for your attention. 2018/11/23