Hakim Weatherspoon CS 3410 Computer Science Cornell University

Slides:



Advertisements
Similar presentations
ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 23 Finite State Machine.
Advertisements

Lab 2: Finite State Machines CS 3410 Spring 2015.
Introduction to Sequential Circuits
State-machine structure (Mealy)
Prof. Kavita Bala and Prof. Hakim Weatherspoon CS 3410, Spring 2014 Computer Science Cornell University See P&H Appendix B.7. B.8, B.10, B.11.
State & Finite State Machines Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See P&H Appendix C.7. C.8, C.10, C.11.
TOPIC : Finite State Machine(FSM) and Flow Tables UNIT 1 : Modeling Module 1.4 : Modeling Sequential circuits.
Sequential Circuits1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.
Circuits require memory to store intermediate data
State and Finite State Machines
Prof. Hakim Weatherspoon CS 3410, Spring 2015 Computer Science Cornell University See P&H Appendix B.7. B.8, B.10, B.11.
CS 151 Digital Systems Design Lecture 21 Analyzing Sequential Circuits.
Prof. Hakim Weatherspoon CS 3410, Spring 2015 Computer Science Cornell University See P&H Appendix B.7. B.8, B.10, B.11.
CS 151 Digital Systems Design Lecture 37 Register Transfer Level
Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University State & Finite State Machines See: P&H Appendix C.7. C.8, C.10, C.11.
Give qualifications of instructors: DAP
State & Finite State Machines Hakim Weatherspoon CS 3410, Spring 2011 Computer Science Cornell University See P&H Appendix C.7. C.8, C.10, C.11.
ECE 301 – Digital Electronics Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #17)
ECE 331 – Digital Systems Design Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #19)
Digital Logic Design Sequential circuits
Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University Memory See: P&H Appendix C.8, C.9.
Introduction to Sequential Logic Design Finite State-Machine Design.
Lecture 5. Sequential Logic 2 Prof. Taeweon Suh Computer Science Education Korea University 2010 R&E Computer System Education & Research.
DLD Lecture 26 Finite State Machine Design Procedure.
Digital Logic Design.
Finite State Machines Prof. Sirer COMP 303 Koç University.
Sequential Circuit: Analysis BIL- 223 Logic Circuit Design Ege University Department of Computer Engineering.
Registers; State Machines Analysis Section 7-1 Section 5-4.
University of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell State Machines.
1 ENGG 1015 Tutorial Three Examples of Finite State Machines Supplementary notes Learning Objectives  Learn about Design of Finite State Machines Ack.:
Prof. Kavita Bala and Prof. Hakim Weatherspoon CS 3410, Spring 2014 Computer Science Cornell University See P&H Appendix B.7. B.8, B.10, B.11.
Introduction to Sequential Logic Design Finite State-Machine Analysis.
Dr. ClincyLecture Slide 1 CS Chapter 3 (3A and ) Part 8 of 8 Dr. Clincy Professor of CS.
Counters and registers Eng.Maha Alqubali. Registers Registers are groups of flip-flops, where each flip- flop is capable of storing one bit of information.
Logic Design (CE1111 ) Lecture 6 (Chapter 6) Registers &Counters Prepared by Dr. Lamiaa Elshenawy 1.
5.3 Sequential Circuits - An Introduction to Informatics WMN Lab. Hey-Jin Lee.
Presentation on Digital Door Lock Digital System Design Presenter: Subash Chandra Pakhrin 072MSI616 MSC in Information and Comm. Engineering Pulchowk Campus.
Digital Design - Sequential Logic Design
Lecture 4. Sequential Logic #2
Introduction to Sequential Logic Design
Introduction to Advanced Digital Design (14 Marks)
State & Finite State Machines
Learning Outcome By the end of this chapter, students are expected to be able to: Design State Machine Write Verilog State Machine by Boolean Algebra and.
EKT 221 : Digital 2 COUNTERS.
COMP541 Sequential Logic – 2: Finite State Machines
Digital Design Lecture 9
Dr. Clincy Professor of CS
Asynchronous Inputs of a Flip-Flop
ECE 301 – Digital Electronics
Prof. Hakim Weatherspoon
Jeremy R. Johnson Mon. Apr. 3, 2000
Digital Logic & Design Dr. Waseem Ikram Lecture No. 34.
CSE 140L Discussion Finite State Machines.
Instructor: Alexander Stoytchev
ECE 3130 – Digital Electronics and Design
Chapter 6 – Part 4 SYEN 3330 Digital Systems SYEN 3330 Digital Systems
CSE 370 – Winter Sequential Logic-2 - 1
Instructor: Alexander Stoytchev
Lecture 15 Logistics Last lecture Today HW4 is due today
Introduction to Sequential Circuits
Lecture 17 Logistics Last lecture Today HW5 due on Wednesday
Guest Lecture by David Johnston
SYEN 3330 Digital Systems Chapter 6 – Part 3 SYEN 3330 Digital Systems.
Lecture 20 Logistics Last lecture Today HW6 due Wednesday
Lecture 17 Logistics Last lecture Today HW5 due on Wednesday
Instructor: Alexander Stoytchev
Lecture 22 Logistics Last lecture Today HW7 is due on Friday
Lecture 22 Logistics Last lecture Today HW7 is due on Friday
CSE 370 – Winter Sequential Logic-2 - 1
Lecture 4: Finite State Machines
Presentation transcript:

Hakim Weatherspoon CS 3410 Computer Science Cornell University Finite State Machines Hakim Weatherspoon CS 3410 Computer Science Cornell University The slides are the product of many rounds of teaching CS 3410 by Professors Weatherspoon, Bala, Bracy, and Sirer.

Goals for Today Finite State Machines (FSM) How do we design logic circuits with state? Types of FSMs: Mealy and Moore Machines Examples: Serial Adder and a Digital Door Lock

Finite State Machines

Next Goal How do we design logic circuits with state?

Finite State Machines An electronic machine which has external inputs externally visible outputs internal state Output and next state depend on inputs current state

Abstract Model of FSM Machine is M = ( S, I, O,  ) S: Finite set of states I: Finite set of inputs O: Finite set of outputs : State transition function Next state depends on present input and present state

Automata Model Finite State Machine Current State Output inputs from external world outputs to external world internal state combinational logic Current State Comb. Logic Registers Output Input Next State Put sequential logic term on slide

FSM Example A B C D Input: up or down Output: on or off down/on down/on input/output up/off A B state start state up/off up/off Legend up/off C D down/off Input: up or down Output: on or off States: A, B, C, or D down/off

FSM Example A B C D Input: = up or = down Output: = on or = off down/on down/on input/output up/off A B state start state up/off up/off Legend up/off C D down/off Input: = up or = down Output: = on or = off States: = A, = B, = C, or = D down/off Say left of slash is input and right is output

FSM Example 1/1 1/1 0/0 0/0 0/0 0/0 1/0 Input: 0=up or 1=down i0i1i2…/o0o1o2… 00 01 S1S0 S1S0 0/0 0/0 Legend 0/0 10 11 1/0 Input: 0=up or 1=down Output: 1=on or 0=off States: 00=A, 01=B, 10=C, or 11=D 1/0

Mealy Machine General Case: Mealy Machine Outputs and next state depend on both current state and input Current State Comb. Logic Registers Output Input Next State

Moore Machine Special Case: Moore Machine Outputs depend only on current state Current State Comb. Logic Registers Output Comb. Logic Input Next State

Moore Machine FSM Example down down input up A off B on state out startout down up Legend up C off D off up down Input: up or down Output: on or off States: A, B, C, or D Also show a mealy machine

Mealy Machine FSM Example down/on down/on input/output up/off A B state start state down/off up/off Legend up/off C D up/off Input: up or down Output: on or off States: A, B, C, or D down/off

Activity#2: Create a Logic Circuit for a Serial Adder Add two infinite input bit streams streams are sent with least-significant-bit (lsb) first How many states are needed to represent FSM? Draw and Fill in FSM diagram Sum: output …10110 …00101 …01111 Strategy: (1) Draw a state diagram (e.g. Mealy Machine) (2) Write output and next-state tables (3) Encode states, inputs, and outputs as bits (4) Determine logic equations for next state and outputs Ask as a clicker question

FSM: State Diagram …10110 …00101 …01111 states: Inputs: ??? and ??? Is this a mealy or moore machine, maybe clicker states: Inputs: ??? and ??? Output: ??? .

FSM: State Diagram __/_ __/_ __/_ __/_ __/_ __/_ __/_ __/_ …10110 …00101 …01111 Is this a mealy or moore machine, maybe clicker states: Inputs: ??? and ??? Output: ??? .

FSM: State Diagram (2) Write down all input and state combinations __/_ __/_ __/_ S0 S1 __/_ __/_ __/_ __/_ __/_ ?? Current state ? Next state (2) Write down all input and state combinations

FSM: State Diagram (3) Encode states, inputs, and outputs as bits __/_ ?? Current state ? Next state (3) Encode states, inputs, and outputs as bits

FSM: State Diagram ?? Current state ? Next state (4) Determine logic equations for next state and outputs

Example: Digital Door Lock Inputs: keycodes from keypad clock Outputs: “unlock” signal display how many keys pressed so far

Door Lock: Inputs Assumptions: K A B signals are synchronized to clock Password is B-A-B K A B Meaning Ø (no key) 1 ‘A’ pressed ‘B’ pressed K A B How many states, another clicker question

Door Lock: Outputs Assumptions: U High pulse on U unlocks door LED dec 4 8 D3D2D1D0 U Strategy: (1) Draw a state diagram (e.g. Moore Machine) (2) Write output and next-state tables (3) Encode states, inputs, and outputs as bits (4) Determine logic equations for next state and outputs

Door Lock: Simplified State Diagram (1) Draw a state diagram (e.g. Moore Machine)

Door Lock: Simplified State Diagram any Cur. State Output (2) Write output and next-state tables

Door Lock: Simplified State Diagram Cur. State Input Next State Cur. State Input Next State “B” G3 G2 ”3”, U ”2” else any Ø (2) Write output and next-state tables

Door Lock: Implementation 4 D3-0 dec S2-0 3bit Reg U clk S2-0 K S’2-0 S2 S1 S0 D3 D2 D1 D0 U A B (4) Determine logic equations for next state and outputs

Door Lock: Implementation S2 S1 S0 S’2 S’1 S’0 K A B 4 D3-0 dec S2-0 3bit Reg U clk S2-0 K S’2-0 A B Write down and compare S2’ (4) Determine logic equations for next state and outputs

Door Lock: Implementation 4 D3-0 dec S2-0 3bit Reg U clk S2-0 K S’2-0 A B Strategy: (1) Draw a state diagram (e.g. Moore Machine) (2) Write output and next-state tables (3) Encode states, inputs, and outputs as bits (4) Determine logic equations for next state and outputs

Door Lock: Implementation Current State Comb. Logic Registers Output Comb. Logic Input Next State Moore Machine Strategy: (1) Draw a state diagram (e.g. Moore Machine) (2) Write output and next-state tables (3) Encode states, inputs, and outputs as bits (4) Determine logic equations for next state and outputs

Goals for today Review Finite State Machines

Summary We can now build interesting devices with sensors Using combinational logic We can also store data values Stateful circuit elements (D Flip Flops, Registers, …) State Machines or Ad-Hoc Circuits